Verifying Layered Protocols
– Leveraging Advanced UVM
Capabilities
Parag Goel
Sr. Corporate Application Engineer
Synopsys India Pvt. Ltd.
Stack based architecture
– Reasons for adoption
Signaling
Breaking network
Interconnect
Application 7
Transaction Fragments Adaptation Layer
Presentation 6
designs into functional Session 5
layers Transport
Packets
4
SAP-based
communication
Enables each layer to be LLI Stack
Specification
Network 3
governed by simple protocols Data Link
Frames
2
Each with a few well-defined Physical
PHITs -> Symbols
1
tasks Physical Media
Easier Debug
Faster convergence to where network failures originate
The same user-level (application) program can be
used over diverse communication networks.
Same WWW browser can be used when you are connected to the
internet via a LAN or a dial-up line.
Agenda
Verification IP & Testbench Challenges
Architectural Challenges
Stimulus generation - Generate varied traffic corresponding to each layer
Visibility and granularity of control - retrieving transaction for analysis
Support for intermediate layer and multi-lane scenarios
Application Challenges
Verifying Transformations
Graceful End-of-test
Enough debugging hooks
Need to map verification challenges to existing
methodologies
Leverage available methodology capabilities
Build intelligent layers around base classes for more powerful verification setup
Architectural Challenges - I
- Stimulus Generation Ability to inject stimulus at
AXI/AHB/OCP etc..
any layer
One-to-Many
Interconnect Transactions Upstream Protocol
S
T It should be possible to
A
Fragment ... Fragment C configure any of the layers as
K
top-most layer generating the
Fragment CRC T
R
A
highest upstream sequence.
PHIT Header Packet Header N
Frame Header
S
F
PHIT(96 bit vector) O
R
Ability to arbitrate, i.e. mix
PHY Symbol[0] ...
S
PHY Symbol[11]
M
A and match stimulus from
8-bit E 8-bit T
Many-to-One R
I
A
T
I the upper layer as well as
Downstream Protocol O
L N
from the testbench
Ability to retrieve and modify the transaction at any specific layer
via callbacks, factory mechanism and UVM command-line
override.
Architectural Challenges - II
- Verifying intermediate layer
Traffic DUT Traffic
towards L3/L2 towards L1/L2
Custom Custom
VIP User defined User defined VIP
L2
End-End
checking
or
L2 Tx L1 Tx
Layered - VIP Layered– VIP
Serial
Transactions / L L Transactions /
sequences
L2 L1 /TLM L1 L2
3 sequences
3
Appropriate hooks/callbacks/ports for each component
Retrieve the transactions from any layer
Provision to hook up intermediate custom drivers which can
then drive the interface between the layers.
Callbacks across monitors to verify transformations across the
layers.
Architectural Challenges - III
- Verifying multi-lane scenarios
Interconnect Adaption
pa_lane_seqr[0] Layer
pa_lane_seqr[1] Transaction Layer
….. Data Link Layer
…..
……. Physical Adaptor Layer
pa_lane_seqr[n]
Sequencer Definition
typedef class
uvm_sequencer#(mphy_transfer)
Expanded version mphy_sequencer;
. Multiple TLM
. ………………………
of l3_sequencer – Ports M-
composed of sub- M- M- M-
RX[0]
sequencer per M-
RX[0] M-
RX[0] . .Instances
………………………of
TX[n]
lane TX[0] TX[1] PHY/per lane
Pair of TX-RX Serial
. . ………………………
transactors Interface
class lli_agent extends uvm_agent;
Sequencer Handle Declaration – Dynamic Array
mphy_sequencer pa_lane_seqr[];
function void build_phase(uvm_phase phase);
if(!uvm_config_db#(lli_configuration)::get(this, “”, “cfg”, cfg)) `uvm_fatal(………….)
Sequencer creation
pa_lane_seqr = new[cfg.tx_lane_count];
foreach(pa_lane_seqr[i])
pa_lane_seqr[i] = mphy_sequencer::type_id::create($sformatf(“pa_lane_seqr[%0d]”, i), this);
endfunction
endclass
Addressing Architectural challenges - I
- Generic architecture
Class & UVM factory Registration
class generic_sequence#(type REQ=uvm_seqence_item,
l1_sequence l1_sequencer l1_sequencer type RSP=REQ) extends uvm_sequence#(REQ,RSP);
Layer-I (L1) `uvm_object_param_utils(generic_sequence#(REQ,RSP))
Common
Processing Code
generic_sequen
ce
Parent Sequencer Declaration
l2_sequence l2_sequencer l2_sequencer
`uvm_declare_p_sequencer(uvm_sequencer#(REQ))
Virtual Transaction Handle
Layer-II (L2)
Sequencer Common local REQ req;
Processing Code
generic_sequen
l3_sequencer l3_sequencer ce
l3_sequence
Dispatch: Drive REQ on downstream sequencer
task dispatch(uvm_seqeuncer#(REQ) seqr, REQ req);
this.req = req;
Layer-III (L3) this.start(seqr);
Common
endtask
Processing Code
Body method – Initiate REQ
task body();
if (this.req != null) begin
response_handler method – To discard RSP this.wait_for_grant();
function void response_handler this.send_request(req);
(uvm_sequence_item response); this.wait_for_item_done();
/* Just drop the response. */ end
endfunction endtask
endclass
Addressing Architectural challenges - II
- Generic architecture – Flow Diagram
Passed to the
l1_rsp_seqr to Consumed
Form
l1 Transmit Request Response by
Input l1_seq_item via. Response
Path testbench
l1_seqr
Process Send out to
l1_seq_item -> l2_seq_item testbench
blk_peek_port.connect(bl
k_peek_export)
Process & Call
Input l2_seq_item via. Call blk_peek_port.peek(l1_seq_item)
l2_seqr generic_seq.dispatch(l2_seqr, l2_seq_item)
Accept
task put(l1_sequence_item l1_seq_item)
l2_seqr blk_put_port.connect
(blk_put_export)
Process
Call
l2_seq_item -> l3_seq_item
blk_put_port.put(l1_seq_item)
Call Process
Input l3_seq_item via.
generic_seq.dispatch(l3_seqr, l3_seq_item) l2_seq_item -> l1_seq_item
l3_seqr
Accept
task put(l2_sequence_item l2_seq_item)
l3_seqr blk_put_port.connect
Process (blk_put_export)
l2_seq_item -> l3_seq_item Call
blk_put_port.put(l2_seq_item)
Process
Drive interface
l3_seq_item -> l2_seq_item
Sample interface & form
l3_seq_item
TRANSMIT RECEIVE
FLOW FLOW
Application Challenges - I
- Scoreboarding Challenges - I
… Scoreboarding @
IAL
Scoreboarding @ Classified for
… 1. Request/Response
IAL-TL-DLL-PAL Layers TL 2. All traffic types
…
DL
… …
IAL PAL
REQ RSP
SQNR SQNR … LLI
TL Passive
IAL … Monitor
STACKED
DL
Frag DeFrag
… DUT
PAL
TL+DL+PAL Physical Interface
Monitor
Transformations that would need to be verified
End to end transformations in the ‘transmit’ and ‘receive’ paths
Transformations across all the traffic types
For requests / responses
Application Challenges - I
- Scoreboarding Challenges -
1
Request
Request
Received
Transmitted
Response
3 2 Generated
Response
Received
STACK - I STACK - II
Response
Received
Response
Generated Request
Request Transmitted
Received
Addressing Scoreboarding Challenges
class lli_system_env extends uvm_env;
Policy Based design :
template taking several type typedef lli_scoreboard#(svt_mipi_lli_transaction)
trans_scbd;
parameters typedef lli_scoreboard#(svt_mipi_lli_packet)
specialized to encapsulates pkt_scbd;
orthogonal aspects of the behavior of
An instance of VIP AGENT - LLI Master/Slave
the instantiated class svt_mipi_lli_agent mstr, slv;
class lli_comp #(type T = int); IAL Scoreboard Instances for request xact
static uvm_comparer relevant_comparer = new(); trans_scbd m_s_ll_xact_sb;
static function bit comp(input T a, input T b); trans_scbd m_s_be_xact_sb;
relevant_comparer.physical = 1;
relevant_comparer.abstract = 0; Construct the IAL scoreboard instances
return a.compare(b, relevant_comparer); m_s_ll_xact_sb = new("m_s_ll_xact_sb", this);
endfunction m_s_be_xact_sb = new("m_s_be_xact_sb", this);
endclass
Connect the monitor to the scoreboard for Master
LL request
mstr.ial_mon.tx_ll_ta_xact_observed_port.
class lli_scoreboard#(type T=uvm_sequence_item) connect(m_s_ll_xact_sb.tx_export);
extends uvm_scoreboard; slv.ial_mon.rx_ll_in_xact_observed_port.
connect(m_s_ll_xact_sb.rx_export);
Export Transmitted/Received Requests
uvm_analysis_export#(T) tx_export, rx_export;
Connect the monitor to the scoreboard for Master
"in order comparator"
BE request
uvm_in_order_comparator #(T, lli_comp#(T),
mstr.ial_mon.tx_be_ta_xact_observed_port.
uvm_class_converter#(T)) comparator;
connect(m_s_be_xact_sb.tx_export);
slv.ial_mon.rx_be_in_xact_observed_port.
Building components
connect(m_s_be_xact_sb.rx_export);
Connect local export to comparator export
endclass
Reporting results
Application Challenges - II For a reactive sequence, drop
the objection - response
passed down on the transmit
- End-of-test Mechanism path
Raise/drop objection Raise an objection
in the REQ Sequence RSP Sequence when request
req_sequence’s REQ Sequence RSP Sequence appears on the
pre_body() and receive path.
post_body() REQ SQNR RSP SQNR
Drop objections once
Raise an objection in the peer stack
a callback - the generates the response
request gets and the same is
REQUEST RESPONSE REQUEST RESPONSE
accepted by the received
highest layer
TRANSMIT PATH: RECEIVE PATH:
Raise an objection when new REQ started Raise an objection when new REQ received
Drop an objection when RSP is received Drop an objection when RSP is transmitted
Drain Time - Amount of time to wait once
all objections have been dropped
Global timeout - The phase ends if the timeout
int stack_round_trip_time;
expires even before all objections are dropped
`define HS_MODE_GLOBAL_TIMEOUT 5ms
task main_phase(uvm_phase phase); `define LS_MODE_GLOBAL_TIMEOUT 25ms
phase.phase_done.set_drain_time
(this, 2*stack_round_trip_time); function void test_base::build_phase(...);
endtask Set the global timeout
if(sys_cfg.mode == LS_MODE)
set_global_timeout(`LS_MODE_GLOBAL_TIMEOUT);
else
set_global_timeout(`HS_MODE_GLOBAL_TIMEOUT);
endfunction
Application Challenges - III
- Debug Abstraction
Tracing the transformation across each layer
• Needs to be captured through TLM ports and dumped for Post processing
Debug abstraction : Dumping of protocol objects
Use transaction IDs to map across transformations
Summary
Layered architecture in network protocols bring in advanced
functionalities but complex verification challenges
Can be mapped across multiple new protocols (the MIPI family, PCIe, USB
etc) and network designs
UVM base classes provides the infrastructure on which
required capabilities can be built
user defined enhancing sequence layering, phase completion tracking,
transformation monitoring
Verification infrastructure should continue to evolve with
added complexity in design
