Module 2: Architecture

Digital Signal Controller

TMS320F28335
Texas Instruments Incorporated
European Customer Training Centre
University of Applied Sciences Zwickau

2-1
 F2833x Block Diagram
Program Bus
ePWM

Boot DMA eCAP

Sectored RAM
A(19-0)
ROM 6 Ch.
Flash eQEP
XINTF

DMA Bus
12-bit ADC

D(31-0) Watchdog

PIE
32-bit R-M-W Interrupt CAN 2.0B
32x32 bit Manager
Auxiliary Atomic FPU
Multiplier I2C
Registers ALU
3
Real-Time SCI
32-bit
JTAG Register Bus Timers SPI
Emulation CPU
McBSP
Data Bus
GPIO
2-2
 F2833x CPU
Program Bus

Data Read Bus

32-bit R-M-W
32x32 bit
Auxiliary Atomic FPU
Multiplier
Registers ALU 3 PIE
32-bit Interrupt
Register Bus Manager
Timers

CPU

Data Write Bus

 32-bit fixed and floating point DSP ; 32 x 32 bit fixed-point MAC

 Additional 32 x 32 bit hardware floating point unit
Real-Time
 Dual 16 x 16 single-cycle fixed-point MAC (DMAC)
JTAG
 32-/64-bit saturation Emulation
 Unique real-time debugging capabilities
2-3
 F2833x Fixed Point Multiplier and ALU
Program Bus
32
Data Bus
XT (32) or T/TL 16/32
16 8/16/32
MULTIPLIER
32 32 x 32 or
Shift R/L (0-16) Dual 16 x 16
P (32) or PH/PL 8/16
32
32
32
32 Shift R/L (0-16)

32

ALU (32)
32
ACC (32)
AH (16) AL (16)
AH.MSB AH.LSB AL.MSB AL.LSB

• 32
Shift R/L (0-16)
32
Data Bus
2-4
 F2833x Floating Point Unit FPU
Fixed Point Floating Point

32-bit C28 Register Set FPU Register Set

ACC
Accumulator, R0H
Product,
P 32-bit
XT
Temporary and R1H
8 Auxiliary XAR0 8 FPU Result
XAR1 R2H Registers
Registers
XAR2
R3H
XAR3 FPU Status
XAR4 R4H Repeat Block
XAR5
22-bit R5H
XAR6
Program Counter
XAR7
Return PC R6H
PC
RPC R7H
DP
SP STF
16-bit
ST0
RB
Data Page Pointer ST1
IER
Stack Pointer
IFR
DBGIER R0H – R7H And STF Are Shadowed For Fast
2 Status Context Save And Restore
Interrupt Enable
Interrupt Flag
2-5
 F2833x Pointer, DP and Memory
Data Bus
Program Bus

6 LSB
XAR0 DP (16) from IR
XAR1
XAR2
32 22
XAR3
XAR4 MUX
XAR5
XAR6
XAR7
MUX

ARAU

Data Memory
XARn  32-bits
ARn  16-bits

2-6
 F2833x Internal Bus Structure

Program Program Address Bus (22)

PC
Program-read Data Bus (32) Program
Decoder
Memory
Data-read Address Bus (32)

Data-read Data Bus (32)

Data
Registers Execution Debug Memory
ARAU MPY32x32 FPU
SP Real-Time
ALU R-M-W
DP @X Atomic R0H JTAG
XAR0 XT to Emulation
P ALU Peripherals
to R7H
XAR7 ACC

Register Bus / Result Bus

External
Data/Program-write Data Bus (32) Interface

Data-write Address Bus (32)

2-7
 F2833x Direct Memory Access

PIE
DINTCH1-6
ADC XINTF
Result 0-15 Zone 0, 6, 7

DMA
L4 SARAM 6-channels
McBSP-A
Triggers
L5 SARAM McBSP-B
SEQ1INT / SEQ2INT
MXEVTA / MREVTA PWM1
L6 SARAM MXEVTB / MREVTB
XINT1-7 / 13 PWM2
TINT0 / 1 / 2 PWM3
L7 SARAM PWM4
PWM5
PWM6
SysCtrlRegs.MAPCNF.bit.MAPCNF
(re-maps PWM regs from PF1 to PF3)

2-8
 F2833x Atomic Read/Modify/Write

 Atomic Instructions Benefits:

LOAD  Simpler programming
READ

 Smaller, faster code

Registers CPU ALU / MPY Mem
 Uninterruptible (Atomic)
WRITE

STORE  More efficient compiler

Standard Load/Store Atomic Read/Modify/Write

DINT
AND *XAR2,#1234h
MOV AL,*XAR2
AND AL,#1234h 2 words / 1 cycles
MOV *XAR2,AL
EINT
6 words / 6 cycles
2-9
 F2833x Pipeline
A F1 F2 D1 D2 R1 R2 E W 8-stage pipeline
B F1 F2 D1 D2 R1 R2 E W

C F1 F2 D1 D2 R1 R2 E W Instructions
F1 F2 D1 D2 R1 R2 E W
‘E’ and ‘G’
D E & G Access
access same
F1 F2 D1 D2 R1 R2 E W sameaddress
memory address
E
F1 F2 D1 D2 R1 R2 E W
F
G F1 F2 D1 D2 R11 R2 R
E2 E
W W
F1 F2 D1 D
D22 R1 RR21 R
E2 W
E W
H
F1: Instruction Address
F2: Instruction Content Protected Pipeline
D1: Decode Instruction  Order of results are as written in
D2: Resolve Operand Addr
R1: Operand Address
source code
R2: Get Operand  Programmer need not worry about
E: CPU doing “real” work
the pipeline
W: store content to memory
2 - 10
 TMS320F2833x Memory Map
Data Program
0x000000 0x010000
M0 SARAM (1Kw)
0x000400 reserved
M1 SARAM (1Kw) 0x100000
0x000800 XINTF Zone 6 (1Mw)
0x000D00 0x200000
PIE Vectors XINTF Zone 7 (1Mw)
0x000E00
(256 w) 0x300000
reserved
PF 0 (6Kw) FLASH (256Kw) Dual Mapped:
0x002000
L0, L1, L2, L3
0x004000 0x33FFF8 PASSWORDS (8w)
XINTF Zone 0 (4Kw) 0x340000
0x005000 reserved
PF 3 (4Kw) 0x380080
0x006000 ADC calibration data
PF 1 (4Kw) reserved 0x380090 CSM Protected:
0x007000 reserved
PF 2 (4Kw) 0x380400 L0, L1, L2, L3,
0x008000 User OTP (1Kw) FLASH, ADC CAL,
L0 SARAM (4Kw) 0x380800
0x009000 reserved OTP
L1 SARAM (4Kw) 0x3F8000
0x00A000 L0 SARAM (4Kw)
L2 SARAM (4Kw) 0x3F9000
0x00B000 L1 SARAM (4Kw)
L3 SARAM (4Kw) 0x3FA000 DMA Accessible:
0x00C000 L2 SARAM (4Kw)
L4 SARAM (4Kw) 0x3FB000 L4, L5, L6, L7,
0x00D000 L3 SARAM (4Kw) XINTF Zone 0, 6, 7
L5 SARAM (4Kw) 0x3FC000
0x00E000 reserved
L6 SARAM (4Kw) 0x3FE000
0x00F000 Boot ROM (8Kw)
L7 SARAM (4Kw)
0x010000 0x3FFFC0 BROM Vectors (64w)
0x3FFFFF
Data Program
2 - 11
 Code Security Module

 Prevents reverse engineering and

protects valuable intellectual property

CSM Protected:
L0, L1, L2, L3,
FLASH, ADC CAL,
OTP

 128-bit user defined password is stored in Flash

 128-bits = 2128 = 3.4 x 1038 possible passwords
 To try 1 password every 2 cycles at 150 MHz, it
would take at least 1.4 x 1023 years to try all
possible combinations!
2 - 12
 F2833x Fast Interrupt Response Manager

 96 dedicated PIE
vectors
 No software decision
making required PIE module 28x CPU Interrupt logic

Peripheral Interrupts 12x8 = 96

For 96
 Direct access to RAM interrupts
vectors INT1 to
INT12 28x
 Auto flags update IFR IER INTM CPU
96
12 interrupts
 Concurrent auto PIE
Register
context save
Map

Auto Context Save

T ST0
AH AL
PH PL
AR1 (L) AR0 (L)
DP ST1
DBSTAT IER
PC(msw) PC(lsw)
2 - 13
 F2833x Operating Modes

Mode Type Mode Bits Compiler Option

OBJMODE AMODE

C28x Native Mode 1 0 -v28

C24x Compatible Mode 1 1 -v28 –m20
Test Mode (default) 0 0
Reserved 0 1

 Almost all uses will run in C28x Native Mode

 The bootloader will automatically select C28x Native Mode after reset
 C24x compatible mode is mostly for backwards compatibility with an
older processor family

2 - 14
 Reset – Bootloader

Reset
OBJMODE = 0 AMODE = 0
ENPIE = 0 INTM = 1

Bootloader sets
OBJMODE = 1
AMODE = 0
Reset vector fetched
from boot ROM Boot determined by
state of GPIO pins
0x3F FFC0

Execution
Entry Point
Note: M0 SARAM
Details of the various boot options will be
discussed in the Reset and Interrupts module

2 - 15
 Highlights of the F2833x

 High performance 32-bit DSP

 32x32 bit or dual 16x16 bit MAC
 IEEE single-precision floating point unit
 Atomic read-modify-write instructions
 Fast interrupt response manager
 256Kw on-chip flash memory
 Code security module (CSM)
 Control peripherals
 12-bit ADC module
 Up to 88 shared GPIO pins
 Watchdog timer
 DMA and external memory interface
 Communications peripherals
2 - 16