Scribd
Upload
114 views9 pages

High-Speed Configurable Adder For Approximate Computing

The document proposes a high-speed configurable adder for approximate computing. Approximate computing trades accuracy for power efficiency in error-tolerant applications. The proposed adder maintains small area while providing configurable accuracy through run-time carry propagation masking. Experimental results show the adder delivers significant speedup with small area overhead compared to conventional carry lookahead adders.

Uploaded by

vishwas
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
114 views9 pages

High-Speed Configurable Adder For Approximate Computing

The document proposes a high-speed configurable adder for approximate computing. Approximate computing trades accuracy for power efficiency in error-tolerant applications. The proposed adder maintains small area while providing configurable accuracy through run-time carry propagation masking. Experimental results show the adder delivers significant speedup with small area overhead compared to conventional carry lookahead adders.

Uploaded by

vishwas
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
You are on page 1/ 9

High-Speed Configurable Adder

for Approximate Computing


ABSTRACT
Approximate computing is an efficient approach for
error-tolerant applications because it can trade off
accuracy for power. Addition is a key fundamental
function for these applications. In this paper, we
proposed a high speed accuracy-configurable adder
that also maintains a small design area
INTRODUCTION

• Applications that have recently emerged have


created challenges relative to power
consumption. Addition is a fundamental
arithmetic function for these applications.
• In this project, we propose a configurable
approximate adder , which consumes lesser
power than does with a comparable delay and
area
PROPOSED 16 BIT-ADDER
Tools used
Software requirements:
Modelsim 6.4b
Xilinx ISE 13.2
Language used

Verilog
CONCLUSION
In this paper, an accuracy-configurable adder without suffering

the cost of the increase in delay for configurability was

proposed. The proposed adder is based on the conventional

CLA, and its configurability of accuracy is realized by

masking the carry propagation at runtime.


The experimental results demonstrate that the

proposed adder delivers significant speedup

with a small area overhead than those of the

conventional CLA.
References:
[1] S. Cotofana, C. Lageweg, and S. Vassiliadis, “Addition related arithmetic operations
via controlled transport of charge”, IEEE Transactions on Computers, vol. 54, no. 3,
pp. 243-256, Mar. 2005.
[2] V. Beiu, S. Aunet, J. Nyathi, R. R. Rydberg, and W. Ibrahim, “Serial Addition:
Locally Connected Architectures”, IEEE Transactions on Circuits and Systems-I:
Regular papers, vol. 54, no. 11, pp. 2564-2579, Nov. 2007.
[3] S. Venkataramani, V. K. Chippa, S. T. Chakradhar, K. Roy, and A. Raghunathan,
“Quality programmable vector processors for approximate computing”, 46th
Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), pp.
1-12, Dec. 2013.
[4] A. B. Kahng, and S. Kang, “Accuracy-configurable adder for approximate
arithmetic designs”, IEEE/ACM Design Automation Conference (DAC), pp. 820-
825, Jun. 2010.

You might also like