Lecture 2-Computer Evolution and Performance
Lecture 2-Computer Evolution and Performance
Lecture 2
Computer Evolution and
Performance
1
Key Points
The evolution of computers has been
characterized by
Increasing processor speed,
2
Key Points
The processor speed true gains from
organization of the processor using new
techniques, including heavy use of
pipelining and parallel execution
techniques.
All of these techniques are designed to
keep the processor busy as much of the
time as possible.
3
Key Points
A critical issue in computer system design is
balancing the performance of the various
elements.
In particular, processor speed has increased
more rapidly than memory access time.
A variety of techniques is used to
compensate for this mismatch, including
caches, wider data paths from memory to
processor, and more intelligent memory
chips. 4
A BRIEF HISTORY OF COMPUTERS
The First Generation: Vacuum Tubes
The ENIAC (Electronic Numerical
Integrator And Computer), designed and
constructed at the University of
Pennsylvania, was the world’s first general
purpose electronic digital computer.
The project was a response to U.S. needs
during World War II. The Army’s Ballistics
Research Laboratory (BRL)
5
ENIAC - Detail
Started 1943 - Finished 1946
Used until 1955
Decimal (not binary)
20 accumulators of 10 digits
Programmed manually by switches
18,000 vacuum tubes
30 tons
15,000 square feet
140 kW power consumption
5,000 additions per second
ENIAC - Detail
A ring of 10 vacuum tubes represented each
digit.
At any time, only one vacuum tube was in the
ON state, representing one of the 10 digits.
The major drawback of the ENIAC was that it
had to be programmed manually by setting
switches and plugging and unplugging cables.
Von Neumann Machine
Stored Program concept
Main memory storing programs and data
ALU operating on binary data
Control unit interpreting instructions from
memory and executing
Input and output equipment operated by control
unit
Princeton Institute for Advanced Studies
IAS Computer
Completed 1952
Structure of von Neumann machine
2 x 20 bit instructions
Instruction Register
Program Counter
Accumulator
Multiplier Quotient
IAS – Registers
Control Unit and the ALU contain storage
locations, called registers
Memory buffer register (MBR): Contains a
word to be stored in memory or sent to the I/O
unit, or is used to receive a word from memory
or from the I/O unit.
Memory address register (MAR): Specifies the
address in memory of the word to be written
from or read into the MBR.
Instruction register (IR): Contains the 8-bit
opcode instruction being executed.
IAS – Registers
Instruction buffer register (IBR): Employed to
hold temporarily the right hand instruction from
a word in memory.
Program counter (PC): Contains the address of
the next instruction-pair to be fetched from
memory.
Accumulator (AC) and multiplier quotient
(MQ): Employed to hold temporarily operands
and results of ALU operations.
Structure of IAS –
detail
IAS Structure Continue ……
Scientific calculations
Business applications
Cheaper