Microprogrammed Control

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 Microprogrammed Control Unit
• In microprogrammed control unit design, control
signals are generated by a program similar to
machine language programs.
• Control unit stores the values of signals in
memory instead of computing them.
• Every control signal is allocated a bit in memory,
and if the signal is to be 1, the bit will store a 1;
otherwise it will store a 0.
• Suppose that the control unit needs to generate
20 control signals. Then, 20 bits are allocated for
each memory address.
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 Microprogrammed Control Unit
• Each memory address will store the signal values for a
particular clock cycle. For example, memory address 0
will store the signal values for clock cycle T1.
• The word whose bits represent the various control
signals required is called Control Word (CW).
• An individual control word is also called
Microinstruction.
• A Microroutine is sequence of control words
corresponding to control sequence of machine
instruction.
• The Control Store stores microroutines for all
instructions in instruction set of a computer.

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 Microprogrammed Control Unit
• Consider the control sequence for instruction
ADD R1, [R3] (R1← R1 + [R3]) for the single-
bus CPU:

• We can store the required control signals for

this control sequence in memory as follows:

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 General Microprogrammed Control
Unit Organization
• uPC: holds the address
of next contol word to
be fetched from the
control store.
• Incrementer: to
increment the uPC.
• Control Store: to store
the microroutines for all
instructions.
• Microinstruction register
(uIR): to hold the fetched
microinstruction.

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 General Microprogrammed Control
Unit Organization
• Programmable logic array (PLA): mapping opcode field of IR
to starting address of microroutine of instruction.
• 4x1 Multiplexer: The uPC can be loaded from:
– The incremented uPC.
– The output of the PLA.
– An external source. This allows the uPC to be initialized to a
starting value to begin instruction fetch, interrupt service, or
reset.
– Branch address field from the current microinstruction. This
allows unconditional and conditional microbranches.
• Sequencer: combinational circuit to control 4x1 MUX
select lines based on microbranch control signals from
microinstruction and flags.

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 Control Word Format
• The control store contains three
kinds of fields in each control
word:
– Control signal field, C bits: used
to store the control signals such
as PCin, MARout, etc., with 1 bit
for each control signal.
– Branch address field, n bits: used
to store the microbranch
address, where n is the number
of bits in the uPC.
– Branch control field, k bits:
contains various signals to
control branching in microcoded
control unit.

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Branching Controls

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Wilker’s Design : Control field

microinstruction (I) Address field

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How to decide I word length
1. The degree of parallelism required at the micro-operation level
2. How the control information is represented or encoded
3. How to specify the next I address
o Parallelism in I
If all useful combination of parallel micro-operation are specified by a single
opcode it would be enormous, and decoder will be complicated.
→ divide the micro-operation specification part into k disjoint control field, any
one of which can be performed simultaneously with other.
① In IBM 360/50: I 90 bits (21 partitioned control field).
② Wilker design: 1-bit control field for each control signal.

X0 X1 X2 X3 Un-encoded form (4-bit)

c0 c c2 c3 Micro-operation
c0 ○ c1 ○ c2 ○ c3 ○ 1
1 0 0 0 R← X0
Register R 0 1 0 0 R← X1
0 0 1 0 R← X2
0 0 0 1 R← X3
0 0 0 0 No op
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 Encoded form (3-bit)

K0 K1 K2 Micro-operation

0 0 1 R← X0
0 1 0 R← X1
0 1 1 R← X2 5 operations
1 0 0 R← X3
0 0 0 No op

n independent control signal → ⌈log2(n+1)⌉ bits decoder is needed

I : horizontal VS vertical
horizontal form : ① long format
② able to express a high degree of parallelism
③ little encoding for the control information.

vertical form : ① short format

② limited ability to express parallelism
③ considerable encoding of the control information. 11
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Design of 2C multiplier hardwired control

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Twos-complement Multiplication - HDL
Address Microoperations Control Signals
activated
BEGIN: A := 0, COUNT := 0, F := 0, M := INBUS; c9, c10
INPUT: Q := INBUS; c8
TEST1: If Q[0] = 0 then go to RSHIFT:

ADD: A[7:0] := A[7:0] + M[7:0], F := (M[7] and Q[0]) or F; c2, c3, c4

RSHIFT: A[7] := F, A[6:0].Q := A.Q[7:1], COUNT := COUNT + 1, c0, c1, c11
If COUNT7 = 0 then go to TEST1;

TEST2: If Q[0] = 0 then go to OUTPUT1;

SUBTRACT: A[7:0] := A[7:0] – M[7:0], Q[0] := 0; c2, c3, c4, c5

OUTPUT1: OUTBUS := A; c6
OUTPUT2: OUTBUS := Q; c7
END: Halt; END
Address Condition Branch Control Fields
in CM Select Address
C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 END

0000 00 0000 0 0 0 0 0 0 0 0 0 1 1 0 0
0001 00 0000 0 0 0 0 0 0 0 0 1 0 0 0 0
0010 01 0100 0 0 0 0 0 0 0 0 0 0 0 0 0
0011 00 0000 0 0 1 1 1 0 0 0 0 0 0 0 0
0100 10 0010 1 1 0 0 0 0 0 0 0 0 0 1 0
0101 01 0111 0 0 0 0 0 0 0 0 0 0 0 0 0
0110 00 0000 0 0 1 1 1 1 0 0 0 0 0 0 0
0111 00 0000 0 0 0 0 0 0 1 0 0 0 0 0 0
1000 00 0000 0 0 0 0 0 0 0 1 0 0 0 0 0
1001 11 1001 0 0 0 0 0 0 0 0 0 0 0 0 1

Binary Micro-program for Twos-Complement Multiplication 16

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Encoding by function
A drawback of the minimum-width control field : functionally unrelated
control signals are combined.

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END

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5.2 Microprogrammed Control

Instruction
: implemented by a sequence of one or more sets of concurrent micro-operations.

Microprogramming
: control-signal selection and sequencing information is stored in a ROM or RAM
called a control memory(CM), and microinstruction is fetched from CM.

A microprogrammed computer C1 can be used to execute program written in the

machine language L2 of some other computer C2 by placing an emulation for L2 in the
CM of C1.

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