Digital VLSI Design

(ECE314/ ECE514)

Lecture-5

24-Aug-2018
 CMOS Inverter
N Well VDD

VDD PMOS 2l

Contacts
PMOS
In Out
In Out
Metal 1
Polysilicon
NMOS

NMOS
GND

Anuj Grover
Source: Digital Integrated Circuits, J.Rabaey,A Chandrakasan,B Nikolic
 Two Inverters

Share power and ground

Abut cells
VDD
Connect in Metal

Anuj Grover
Source: Digital Integrated Circuits, J.Rabaey,A Chandrakasan,B Nikolic
 2 Inverters – layout with strap
VDD

PMOS

VDD

1.2mm
=2l
Out
In
Metal1

Polysilicon

NMOS
GND

Anuj Grover
Source: Digital Integrated Circuits, J.Rabaey,A Chandrakasan,B Nikolic
 DC Transfer Curve
• Transcribe points onto Vin vs. Vout plot

Vin0 Vin1
VDD Vin2
Vin0 Vin5
A B

Vout
Vin1 Vin4
C

Vin2 Vin3
Vin3
Vin3 Vin2 D Vin4 Vin5
Vin4 Vin1 E
0 Vtn VDD/2 VDD+Vtp
VDD VDD
Vout Vin

Anuj Grover
Source: CMOS VLSI Design, N.Weste; D. Harris
 Beta Ratio
• If bp / bn  1, switching point will move from VDD/2

• Called skewed gate

• Other gates: collapse into equivalent inverter

VDD
bp
 10
bn
Vout 2
1
0.5
bp
 0.1
bn

0
VDD
Vin

Anuj Grover
Source: CMOS VLSI Design, N.Weste; D. Harris
 Delay Definitions
• tpdr: rising propagation delay
• From input to rising output
crossing VDD/2

• tpdf: falling propagation delay

• From input to falling output
crossing VDD/2

• tpd: average propagation delay

• tpd = (tpdr + tpdf)/2

• tr: rise time

• From output crossing 0.2 VDD
to 0.8 VDD

• tf: fall time

• From output crossing 0.8 VDD
to 0.2 VDD
Anuj Grover
Source: CMOS VLSI Design, N.Weste; D. Harris
 Delay Definitions
• tcdr: rising contamination delay
• From input to rising output crossing VDD/2

• tcdf: falling contamination delay

• From input to falling output crossing VDD/2

• tcd: average contamination delay

• tpd = (tcdr + tcdf)/2

Anuj Grover
Source: CMOS VLSI Design, N.Weste; D. Harris
Delay Models

Anuj Grover
 CMOS Inverter Propagation Delay
Approach 1
VDD

tpHL = CL Vswing/2
Iav

Vout CL
~
Iav CL kn VDD

Vin = V DD
Anuj Grover
Source: Digital Integrated Circuits, J.Rabaey,A Chandrakasan,B Nikolic
 CMOS Inverter Propagation Delay
Approach 2
VDD

tpHL = f(Ron.CL)
= 0.69 RonCL

Vout
Vout ln(0.5)
CL
1 VDD
Ron

0.5
0.36

Vin = V DD
t
RonCL
Anuj Grover
Source: Digital Integrated Circuits, J.Rabaey,A Chandrakasan,B Nikolic
 Transient Response
3

2.5
?
2
tp = 0.69 CL (Reqn+Reqp)/2
1.5
Vout(V)

tpLH tpHL
1

0.5

-0.5
0 0.5 1 1.5 2 2.5
t (sec) -10
x 10

Anuj Grover
 Design for Performance
• Keep capacitances small

• Increase transistor sizes

• watch out for self-loading!

• Increase VDD (????)

Anuj Grover
 Delay as a function of VDD

5.5

4.5

4
tp(normalized)

3.5

2.5

1.5

1
0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4
V (V) Anuj Grover
DD
 Device Sizing
-11
x 10
3.8

3.6 (for fixed load)

3.4

3.2
tp(sec)

2.8 Self-loading effect:

2.6 Intrinsic capacitances
2.4 dominate
2.2

2
2 4 6 8 10 12 14
S
Anuj Grover
 NMOS/PMOS ratio
-11
x 10
5

tpLH tpHL
4.5

tp b = Wp/Wn
tp(sec)

3.5

3
1 1.5 2 2.5 3 3.5 4 4.5 5
b

Anuj Grover
 Delay Estimation
• The step response usually looks like a 1st order RC response with a
decaying exponential.

• Use RC delay models to estimate delay

• C = total capacitance on output node
• Use effective resistance R
• So that tpd = RC

• Characterize transistors by finding their effective R

• Depends on average current as gate switches

• Too inaccurate to predict current at any given time

• But good enough to predict RC delay

Anuj Grover
Source: CMOS VLSI Design, N.Weste; D. Harris
 RC Delay Model
• Use equivalent circuits for MOS transistors
• Ideal switch + capacitance and ON resistance
• Unit nMOS has resistance R, capacitance C
• Unit pMOS has resistance 2R, capacitance C

• Capacitance proportional to width

• Resistance inversely proportional to width

d
s
kC
kC
R/k
d 2R/k
d
g k g kC
g k g
s kC kC
kC s
s
d
Anuj Grover
Source: CMOS VLSI Design, N.Weste; D. Harris
 Inverter Delay Estimate
• Estimate the delay of a fanout-of-1 inverter

2C

2C 2C
2C 2C
2 Y 2
A Y
1 1 R C
C
R C C

d = 6RC

Anuj Grover
Source: CMOS VLSI Design, N.Weste; D. Harris
 Delay Model Comparison

Anuj Grover
Source: CMOS VLSI Design, N.Weste; D. Harris
 Example: 3-input NAND
• Sketch a 3-input NAND with transistor widths chosen to achieve
effective rise and fall resistances equal to a unit inverter (R).

2 2 2

3
3

Anuj Grover
Source: CMOS VLSI Design, N.Weste; D. Harris
 22
3-input NAND Caps
• Annotate the 3-input NAND gate with gate and diffusion
capacitance.

2C 2C 2C
2C 2C 2C
2 2 2
2C 2C 2C
9C
3 3C
5C 3C
3C
3
5C 3C
3C
3
5C 3C
3C

Anuj Grover
Source: CMOS VLSI Design, N.Weste; D. Harris
 Elmore Delay
• Pullup or pulldown network modeled as RC ladder

• Elmore delay of RC ladder

R1 R2 R3 RN

C1 C2 C3 CN

t pd  
nodes i
Ri tosourceCi

 R1C1   R1  R2  C2  ...   R1  R2  ...  RN  CN

Anuj Grover
Source: CMOS VLSI Design, N.Weste; D. Harris
 24
Example: 3-input NAND
• Estimate worst-case rising and falling delay of 3-input NAND
driving h identical gates.
2 2 2 Y
3 9C 5hC
n2
3 n1 3C
h copies
3 3C

t pdf   3C   R3    3C   R3  R3    9  5h  C   R3  R3  R3 
t pdr  9  5h  RC
 12  5h  RC

Anuj Grover
Source: CMOS VLSI Design, N.Weste; D. Harris
 Contamination Delay
• Best-case (contamination) delay can be substantially less than
propagation delay.

• Ex: If all three inputs fall simultaneously

2 2 2 Y
3 9C 5hC
n2
3 n1 3C

3 3C

R  5 
tcdr   9  5h  C      3  h  RC
3  3 

Anuj Grover
Source: CMOS VLSI Design, N.Weste; D. Harris
 Diffusion Capacitance
• We assumed contacted diffusion on every s / d.

• Good layout minimizes diffusion area

• Ex: NAND3 layout shares one diffusion contact

• Reduces output capacitance by 2C
• Merged uncontacted diffusion might help too

2C 2C
Shared
Contacted
Diffusion Isolated
Contacted 2 2 2
Merged Diffusion
Uncontacted 3 7C
Diffusion 3 3C

3C 3C 3C 3 3C

Anuj Grover
Source: CMOS VLSI Design, N.Weste; D. Harris
 Layout Comparison
• Which layout is better?

VDD VDD
A B A B

Y Y

GND GND

Anuj Grover
Source: CMOS VLSI Design, N.Weste; D. Harris