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05 Binary Operations - R01

The document discusses different binary logic operations including AND, OR, XOR that can be used in ladder logic (LAD), function block diagram (FBD), and statement list (STL) programming. It also covers normally open and normally closed contacts as well as examples of using logic operations to control an output when two sensors are in a certain state.

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thaibkpro
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40 views14 pages

05 Binary Operations - R01

The document discusses different binary logic operations including AND, OR, XOR that can be used in ladder logic (LAD), function block diagram (FBD), and statement list (STL) programming. It also covers normally open and normally closed contacts as well as examples of using logic operations to control an output when two sensors are in a certain state.

Uploaded by

thaibkpro
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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Binary Operations

F1

SIMATIC S7 Date: 04.03.2019


File: 05_.1
Binary Logic Operations: AND, OR
Circuit Diagram LAD FBD STL

S1 (I 0.0)
I 0.0 I 0.1 Q 8.0 I 0.0 & Q 8.0 A I 0.0
= A I 0.1
AND S2 (I 0.1) I 0.1
= Q 8.0
Q 8.1 Q 8.1 = Q 8.1
=

L1 L2
(Q 8.0) (Q 8.1)

(I 0.2) I 0.2 Q 8.2

OR S4 O I 0.3
(I 0.3) =
I 0.3 = Q 8.2
I 0.3

L3 (Q 8.2)

SIMATIC S7 Date: 04.03.2019


File: 05_.2
Binary Logic Operations: Exclusive OR (XOR)

LAD FBD STL

I 0.4 I 0.5 Q 8.0 Q 8.0 A I 0.5


I 0.5 >=1 N
=
O I 0.4
I 0.4 & A I 0.5
I 0.4 I 0.5 I 0.5 N Q8.0
A
=

I 0.4 Q 8.0 X I 0.4


XOR
= X I 0.5
I 0.5 = Q8.0

SIMATIC S7 Date: 04.03.2019


File: 05_.3
Normally Open and Normally Closed Contacts, Sensors and Symbols

Process Interpretation in PLC program

The The sensor Voltage Signal Check for Check for


sensor is ... present state signal state “1” signal state “0”
is a ... at at
input? input Symbol / Result of Symbol / Result of
Instruction check Instruction check

NO activated
contact LAD: LAD:
Yes 1 “Yes“ “No”
1 0
“NO contact” “NC contact”

not No
activated 0 “No” “Yes”
0 1
FBD: FBD:

& &
NC activated No
contact 0 “No” “Yes”
0 1

not STL: STL:


activated Yes 1 “Yes” “No”
A I x.y 1 AN I x.y 0

SIMATIC S7 Date: 04.03.2019


File: 05_.4
Exercise
Task: In all three examples the light should be on when S1 is activated and S2 is not activated!

Hardware

S1 S2 S1 S2 S1 S2

II1.0
1.0 II1.1
1.1 II1.0
1.0 II1.1
1.1 II1.0
1.0 II1.1
1.1
Programmable controller Programmable controller Programmable controller
Q 4.0 Q 4.0 Q 4.0

Light Light Light

Software
I 1.0 I 1.1 Q 4.0 I1.0 I1.1 Q 4.0 I1.0 I1.1 Q 4.0
LAD

I 1.0 & I1.0 & I1.0 &

FDB
I1.1 Q 4.0 I1.1 Q 4.0 I1.1 Q 4.0

....... I1.0 ....... I1.0 ....... I1.0


STL ....... I1.1 ....... I1.1 ....... I1.1
....... Q 4.0 ....... Q 4.0 ....... Q 4.0

SIMATIC S7 Date: 04.03.2019


File: 05_.5
:
:

=
=

A
A
A

SIMATIC S7
I 2.0
AN I 1.1
I 1.0
M3.4

Q 8.1
Q 8.0
M 4.0

0
0
0
0
Signal State

Result of Check

Result of Logic
Operation
Example 1

First Check

File:
Date:
1
1
1
1

05_.6
Signal State

04.03.2019
Result of Check

Result of Logic
Operation
Example 2

First Check
0
1
0
1

Signal State

Result of Check
Result of Logic Operation, First Check. Examples

Result of Logic
Operation
Example 3

First Check
Assignment, Setting, Resetting

LAD FBD STL

I 1.0 I 1.1 Q 8.0 A I 1.0


I 1.0 A I 1.1
& Q 8.0
Assignment ( ) = Q 8.0
I 1.1 =

I 1.2 I 1.3
Q 8.1 I 1.2 A I 1.2
& Q 8.1
Set (S) A I 1.3
I 1.3 S S Q 8.1

I 1.4 Q 8.1
(R) I 1.4 O I 1.4
>=1 Q 8.1 O I 1.5
Reset I 1.5 R R Q 8.1
I 1.5

SIMATIC S7 Date: 04.03.2019


File: 05_.7
Setting / Resetting a Flip Flop

LAD FBD STL

M0.0 M0.0
I1.2 Q 9.3 A I 1.2
SR SR S M 0.0
Dominant S Q I1.2 S
Reset A I 1.3
Q9.3 R M 0.0
I1.3
R Q = A M 0.0
R I1.3 = Q 9.3

M0.0 M0.0
I1.3 Q 9.3 A I 1.3
Dominant RS RS R M 0.0
R Q I1.3 R
Set A I 1.2
Q9.3 S M 0.0
I1.2
Q = A M 0.0
S I1.2 S = Q 9.3

SIMATIC S7 Date: 04.03.2019


File: 05_.8
Midline Output Coil

LAD STL

I 1.0 I 1.1 M0.0 I 2.0 I 2.1 M 1.1 Q 4.0


( ) NOT ( ) ( ) A I 1.0
A I 1.1
= M 0.0
A M 0.0
FBD A I 2.0
A I 2.1
NOT
I 1.0 & = M 1.1
M0.0
A M 1.1
I 1.1 &
= Q 4.0
I 2.0 M1.1 Q 4.0
I 2.1 =

SIMATIC S7 Date: 04.03.2019


File: 05_.9
Instructions that Affect the RLO

LAD FBD STL

A I 0.0
Q 8.0 I 0.0 & A I 0.1
I 0.0 I0.1 Q 8.0
NOT NOT
NOT ( ) I 0.1 = = Q 8.0

Examples:
STAT 0 – Bit memory
CLR
CLR not available not available = M 0.0

STAT 1 – Bit memory

not available not available


SET
SET
= M 0.1

SIMATIC S7 Date: 04.03.2019


File: 05_.10
RLO - Edge Detection
LAD FBD STL

A I1.0
I1.0 I1.1 M1.0 M8.0 I1.0 &
M1.0 M8.0 A I1.1
P FP M1.0
I1.1 P = = M8.0

I1.0 I1.1 M1.1 M8.1 I1.0 A I 1.0


& M8.1 A I 1.1
M1.1
N FN M1.1
I1.1 N = = M8.1

OB1-Cycle
I1.0

I1.1

RLO
Example
M1.0

M1.1

M8.0
M8.1

SIMATIC S7 Date: 04.03.2019


File: 05_.11
Signal - Edge Detection
LAD FBD STL

I1.1 I1.0 & A I1.0


I1.0 M8.0 I1.1 A (
POS POS M8.0 A I1.1
Q
M1.0 M_BIT = FP
M1.0 M_BIT M1.0
)
I1.1 I1.0 =
I1.0 M8.1 &
I1.1 M8.0
NEG A I1.0
Q NEG M8.1
A (
M1.1 M_BIT M1.1 M_BIT = A I1.1
FN
M1.1
)
I 1.0 =
M8.1
I 1.1

M8.0
OB1 Cycle
M8.1
OB1 Cycle

SIMATIC S7 Date: 04.03.2019


File: 05_.12
Unconditional Jump (Independent of RLO)

LAD FBD STL

Network 1 Network 1 Network 1


NEW1 NEW1
( JMP ) .... JMP JU NEW1

Network 2 Network 2 Network 2


: : :
: : :
: : :
: : :
Network x Network x Network x

NEW1 NEW1

M5.5 I4.7 M69.0 NEW1: AN M5.5


M5.5 & M69.0
( ) AN I4.7
I 4.7 = = M69.0

SIMATIC S7 Date: 04.03.2019


File: 05_.13
Conditional Jump (Dependent on RLO)

LAD FBD STL

I 0.0 I 0.1 NEW1 I0.0 & A I0.0


Jump if NEW1 A I0.1
RLO=1 (JMP) I0.1 JMP JC NEW1

Jump if I 0.2 I 0.3 I0.2 & A I0.2


NEW2 NEW2
RLO=0 A I0.3
(JMPN) I0.3 JMPN JCN NEW2

SIMATIC S7 Date: 04.03.2019


File: 05_.14

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