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Logic Design

This document provides an overview of basics of logic design including Boolean algebra, logic gates, multiplexors, Verilog, and designing an arithmetic logic unit (ALU). It reviews Boolean algebra operators and laws, describes common logic gates and multiplexors, introduces data types and syntax in Verilog, and shows how to construct a basic 1-bit ALU and expand it to 32-bits including designing an ALU control unit.

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56 views21 pages

Logic Design

This document provides an overview of basics of logic design including Boolean algebra, logic gates, multiplexors, Verilog, and designing an arithmetic logic unit (ALU). It reviews Boolean algebra operators and laws, describes common logic gates and multiplexors, introduces data types and syntax in Verilog, and shows how to construct a basic 1-bit ALU and expand it to 32-bits including designing an ALU control unit.

Uploaded by

ramnik20098676
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Basics of Logic Design

Panickos Neophytou
CS0447
11/16 – 11/21
Overview
• Boolean Algebra Review
• Logic Gates
• Multiplexors
• Verilog
• ALU design
Boolean Algebra Review
• Operators
– OR: written as +, e.g. A+B
– AND: written as ·, e.g. A·B
– NOT: written as Ā
• Laws of Boolean Algebra
– Identity: A+0=A and A·1=A
– Zero and One laws: A+1=1 and A·0=0
– Inverse laws: A+Ā=1 and A·Ā=0
– Commutative laws: A+B=B+A and A·B=B·A
– Associative laws: A+(B+C)=(A+B)+C and
A·(B·C)=(A·B) ·C.
– Distributive laws: A·(B+C)=(A·B)+(A·C) and
A+(B·C)=(A+B) ·(A+C)
Logic Gates
• Gate: device that implements basic logic
functions, such as AND or OR.
Multiplexors
• E.g. Two-input multiplexor
C  ( A  S )  (B  S )
A 32bit wide 2-to-1 multiplexor
Introduction to Verilog
• Data types
– wire In Verilog, specifies a combinational signal
– reg In Verilog, a register
• reg [31:0] X
• wire [31:0] X
• Refer to contigious set of bits of a register or
wire by [starting bit: ending bit]
• reg [31:0] registerfile[0:31] :An
array of registers
• Possible values: 0, 1 (true, false), z (unknown).
Verilog
• 4’b0100 : 4-bit constant with value 4, 4’d4
same
• -8’h4 : 8-bit constant with value -4 (in two’s
complement)
• {16{2’b01}} : 32-bit value 01010101…01
• {A[31:16],B[15:0]}
Verilog Operators
• Arithmentic: +,-,*,/
• Logical: &,|,~
• Comparison: ==,!=,>,<,>=,<=
• Shift: <<,>>
• Unary logical ops: &,|,^ (e.g. &A results in
one bit by ANDing all of A’s bit together)
Structure of Verilog Program
• Structured as a set of modules
– Module specifies inputs and outputs
– Body of a module consists:
• Initial constructs
• Assignments
• always constructs
• Instances of other modules
always construct
• Defines an optional list of constructs for
which the block is sensitive
• Reevaluated if any of the specified signals
changes value. If no list is specified the it
is constantly reevevaluted.
Assignments
• Blocking assignment =
– Completed before the next assignment is
carried
• Non-blocking assignment <=
– All right-hand sides of the assignments in an
always block are done simultaneously.
Example
Construction a basic ALU
• A 1-bit ALU
ALU
• Full adder
Full Adder
CarryOut calculator
Sum
• The Sum bit is set when exactly one input
is 1 or when all three inputs are 1.
32-bit ALU adder
ALU in verilog
ALU control unit

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