 Portions To Cover

 Basic Concepts
 RAM memories--Static
 If I want program A to be executed then program A
should be brought to main memory (memory)
 In an ideal case, memory can be fast, large and
inexpensive
 Trade offs:
 Increased speed and size are achieved at increased cost
 Decreased cost will result in decreased speed and size
 What we will study?
 Components and organization that make up memory

 Examine memory speed and how to improve the speed

 Basic Concepts:
 Its time to recollect byte addressability and Endianness
 How memory is organized
 ?
 Organized as words (Diagram)
 Byte is a constant entity---1 byte=8 bits
 Word is a variable entity--- 1 word can be 2 bytes, 4 bytes, 8 bytes
 Ex: Let’s take 8086 whose ALU is 16-bit, address bus—20 bit, data bus—
16 bit, Little Endian, Memory byte addressable
 Word size
 ?
 Word size—16 bits (2 bytes)
 How many locations can be addressed?
 2^20 locations can be addressed (In general if the address is n-bit then 2^n
locations can be addressed)
 Address space ?
 Number of addressable locations=2^20
Word 0 0 B1 1 B0
Word 1 2 B3 3 B2
Word 2 4 B5 5 B4
……… 6 …………………… 7 …………………………….
……… 8 ……………. 9 ……………………
……… …………………………. …………………………..
……… ………………………….. ………………………….
……… ………………………… …………………………….
Word 0 0000000000000000000 0000000000000000000
Word 1 0 B1 1 B0
Word 2 0000000000000000001 0000000000000000001
0 B3 1 B2
………
4 B5 5 B4
………
6 …………………… 7 …………………………….
………
8 ……………. 9 ……………………
………
…………………………. …………………………..
………
………………………….. ………………………….
………………………… …………………………….
 Byte addresses: (Accessing a byte in memory)
 How many bits are required to identify a byte in a word
 ?
 How many bytes in a word---2
 So one bit is enough to identify a byte in a word
 In bytes B1, B0 the first 19 bits are same since they belong to the
same word
 Similarly with B2, B0 and so on
 What we can say w.r.t to word 0 is first 19 bits of the address are
used to identify the word word 0 and the last bit is used to identify
a byte in this word(0---B1, 1---B0)
 In general, 19 bits are used to identify a word in memory and 1 bit
is used to identify a particular byte in a word
 Word addresses: (Accessing a word in memory)
 Word 0---00000H
 Word 1---00002H and so on
 Pbm:
 1. Let’s take a machine whose ALU is 32 bit, address
bus-32 bit, data bus—32 bit, Memory byte addressable,
Big endian
 2. Let’s take a machine whose ALU is 64 bit, address
bus-64 bit, data bus—64 bit, Memory byte addressable,
Big endian
 For problems 1 and 2
 Calculate word size, address space
 How many bits are used to identify a word in memory
and how many bits to identify a byte in a word
 How many addressable words?
 Modern computers are byte addressable
 68000 processor ---Big endian
 8086 processor--- Little endian
 In a memory access one word is stored or retrieved
(Word addresses)
 Word 0--- Acc to 8086, word address 00000H is sent to
the memory
 It is also possible to store or retrieve a byte (byte
addresses)
 Connection between memory and processor (Traditional
architecture)
 Data transfer b/w processor and memory takes place thru
MAR, MDR
 MAR is k bits long, address bus—k bits then the no of
addressable locs is 2^k
 MDR is n-bits, data bus—n bits then the word length=n
bits
 Data bus, address bus, control bus---System bus
 In the control bus we have R/W’ signals, MFC (Memory
Function Completed) signal to coordinate data transfers
 R—Read is an Active high signal
 W’—Write is an Active low signal
 How read operation is performed
?
 Address of ML is loaded into MAR and the control line
R/W’ is set to 1
 Memory places data on data lines and MFC is asserted to
indicate this
 Upon receiving this processor loads data on data bus into
MDR
 How write operation is performed ?
 Address of ML is loaded into MAR, data to be written is
loaded into MDR and the control line R/W’ is set to 0
 Processor places data on data lines and is written to
memory which is confirmed by assertion of MFC
 If you want to read from or write into 10 consecutive MLs
then a block transfer is performed where only the address of
the first location is specified
 A useful measure of memory speed is memory access time

?

 Time elapsed between initiation of memory operation and the

completion of that operation
 Ex: time between Read signal and MFC signal

 Another measure is Memory cycle time

 Time delay between initiation of 2 successive memory

operations
 Ex: time delay between 2 successive read operations

 MCT is slightly greater than MAT

 When a memory unit is called RAM
?
 When same fixed amount of time is taken to access any word
in memory
 This distinguishes RAM from magnetic disks, tapes where
time taken to access depends on the position or location
 Basic technology used to implement memories semiconductor
Ics
 Cache memory:
 Memory access time can be reduced by having a cache
memory (small, fast)
 It is between processor and main memory
 How
?
 It holds currently active segments of a program
 The address generated by the processor is called logical
address not physical address
 But what is required is physical address
 There will be a unit MMU(Memory Management Unit)
that translates the logical address to physical address
(actual address)
 Physical address is used to access physical main memory
 MMU is located in processor
?
 Using Mapping function (Later)
 Next Slide
 Virtual Memory
 A memory that appears to be there but not physically present

 It just gives the user a feeling that the size of physical main
memory is increased
?

 With the support of primary storage (HDD)

 When virtual memory will be getting low?

 Virtual memory is a feature of OS but requires MMU for it to

be possible
 The address space of virtual memory is called virtual address
space
 The addresses in virtual address space are called virtual
addresses
 At a given time, not all the virtual addresses are mapped
onto physical memory locations
 Only the active portion of the space is mapped
 The other virtual addresses are mapped to primary
storage (Secondary memory)
 VM---How it works?
 If the desired word is not in physical main memory then
page of words containing the desired word is swapped in
from disk to memory and the page to be swapped out is
judiciously chosen so that swap in, swap out of pages
should not happen frequently (If it happens there will be
a speed degradation)
 Will be studied in detail later
 Semiconductor RAM memories:
 Semiconductor memories are available in wide range of
speeds
 Cycle times: 100ns to <10ns
 Initially they were costlier

 But because of VLSI they dropped down

 They are used in implementing memories
 Internal organization of memory chips:
 Memory cells are organized in the form of an array
 Each cell capable of storing 1 bit
 Next Slide

 This is a very small memory chip
 There are 16 words (W0-W15) in this organization each of
which is of 8 bits
 There are 16 rows each row having 8 cells
 The organization is 16*8
 Each row of cells constitute a memory word
 Each row of cells is connected to a common line called word
line
 Address decoder is there to drive the word lines
 Why 4-bit address decoder (16 word lines)
 When a word line is driven all the cells connected to the word
line are driven
 The cells in each column are connected to a Sense/Write
circuit by 2 bit lines b and b’ (They are complement of one
another)
 These circuits are connected to data input/output lines
 Read operation:
 Address of the word to be read is given as inputs to the address
decoder thru 4 address lines A3 A2 A1 A0
 A word line is driven by the address decoder
 The corresponding cells are driven/selected by the word line
 The R/W’ control line is set to 1 for read operation
 The sense/write circuits select b or b’ for each cell and make them
appear at the data output lines b7-b0
 Write operation:
 Address of the word to be written is given as inputs to the address
decoder
 A word line is driven by the address decoder
 The corresponding cells are selected by the word line
 The R/W’ control line is set to 0 for write operation
 The sense/write circuits receive info and store the info in the
selected cells
 Control lines—2
 Address lines—4
 Data lines---8
 CS—Chip Select selects a chip in multi chip system
 Memory circuit stores 128 bits(16*8)
 External connections—14(4+2+8)
 2 connections---power supply, ground
 This is simple
 Commercially available chips are large (large no of
memory cells)
 They have diff organization
 Static Memories:
 SRAM cell----1 implementation, 1 realization
 Static memories---Memories that retain their state as long as
power is applied
 Ex: Static RAM(SRAM)
 Dynamic memories---Memories that retain their state for
some time(some milliseconds) after the power is turned off
 After some milliseconds again the memory cells have to
powered to retain their state (Refreshing)
 Ex: Dynamic RAM(DRAM)
 Does this make a significant diff in power consumption?
 Yes since there will be billions of cells in a larger memory
 Implementation 1:
 Box is a latch
 How this latch is formed?
 By cross connecting 2 inverters
 The output of one inverter is given as input to the other
 2 bit lines--- b. b’
 1 word line
 The latch is connected to bit lines by means of T1 and T2
 T1, T2--- Transistors
 Transistor can be used as a switch
 It is a semiconductor device that has 3 terminals
 Bipolar transistor--- Collector, Base, Emitter
 MOSFET– Metal Oxide Semiconductor Field Effect Transistor---
Drain, Gate, Source
 If the wordline is not activated T1 and T2 are opened
 If the wordline is activated, T1 and T2 are closed (Read/Write can
be performed)
 When the cell is said to be in state 1
 When the logic value at Point X is 1 and Point Y is 0
 When the cell is said to be in state 0
 When the logic value at Point X is 0 and Point Y is 1
 Read:
 Word line is activated
 T1 and T2 are closed
 If it is in state 1 then b bit line is high and b’ is low
 If it is instate 0 then b bit line is low and b’ is high
 Sense/Write circuit monitor b, b’ and put the appropriate output
 Write operation:
 Word line is activated
 T1 and T2 are closed
 State of the cell is set by Sense/Write circuit by placing values on b,
b’ bit lines
 CMOS realization of Implementation 1:
 CMOS realization:
 CMOS technology----Complementary Metal Oxide
Semiconductor technology
 To construct Ics
 It is used in microprocessors, SRAMs
 Things that are same as Implementation 1 bit lines(b,b’), word
line, T1, T2
 Four transistors--- T3, T4, T5, T6
 T3,T5 pair forms one inverter
 T4, T6 forms another inverter of Implementation 1
 In the implementation, output of one inverter is given to input
of another inverter
 How is this achieved here
 By the cross lines
 Situation:
 Lets say cell is in state 1
 Logic 1 at point X
 Logic 0 at point Y
 How this state is retained
 Logic 1 at point X turns on the transistor T6, T4(turned off)
 Logic 0 at point Y turns on the transistor T3, T5(turned off)
 Even after T1, T2 are turned off the transistors T3, T6 are turned on because of the supply
 That is how the state is retained
 Situation 2:
 Lets say cell is in state 0
 You provide explanation
 In older CMOS SRAM power supply voltage is 5V
 In newer versions power supply voltage is 3.3V
 Continuous power is required
 If power is interrupted—Cell contents are gone
 SRAMs are volatile memories
 Advantage of CMOS SRAM--- low power consumption
 When the cell is not accessed, T1, T2 are off, one of the transistors in each inverter is off
 SRAMS access time is just a few ns (can be accessed quickly)
 Portions To Cover
 Structure of larger memories
 Memory system considerations
 Larger memories are formed by connecting smaller memory chips
 Static memory systems:
 I am going to construct a larger memory(2M*32) 2M words each of which
is of size 32 bits using (512K*8) memory chips i.e., 512K words each of
which is of size 8 bits
 First let’s determine the no of columns in the organization, then determine
the no of rows
 In a row, How many 512K*8 memory chips ?
 Remember each word in 2M*32 is of length 32 bits
 4*8=32
 In each row I should have four 512K*8 memory chips for each word in
2M*32 to be of size 32 bits
 Columns determined
 To determine how many rows, divide 2M by 512K
 4
 4 rows
 Conclusion: To construct 2M*32 from 512K*8 what I need is 4 rows, each
row having 4 512K*8 memory chips
 Totally 16 512K*8 memory chips are required to build 2M*32
 From the organization you can see that there are 4 rows, each row having
4 512K*8 chips
 It is confirming our estimation
 The address used is 21 bit address
 How many rows are there to be addressed?
 4
 How many bits required to address 4 rows
 2 bits
 The first 2 bits of 21 bit address are used for this purpose
 How many words are to be addressed (At a time only one row is active)
 ?
 512K=524288
 How many bits?
 19 bits since 2^19=524288
 The lower order 19 bits of 21-bit address are used to access a word
 Conclusion: 2 bits are used to select a row and 19 bits are used to select a
word in that row
 2 bit decoder is used to select a row
 According to this organization only a row of memory chips
can be selected
 You cant select a particular memory chip in a row
 About chip select
 When the input to decoder is 00, first row is activated
 It is your CS(Chip Select) control signal that selects all the
memory chips in that row
 4 groups of data lines: D31-D24 and so on
 Data output/input:
 so that data can be accepted from (write) or put onto (read)
 Each group (D31-D24) has 8 data lines (512K*8)
 The data input/output of unselected chips are in high
impedance state
 Dynamic memory systems:
 Organization of larger dynamic memory systems is the same as your larger
static memory systems
 Physical implementation is different
 It is done in the form of memory modules
 Modern computers have large memories
 Adv?
 More of the programs and data used in processing can be held in memory
 If a larger dynamic memory is built by placing the DRAM chips on the mother
board it will occupy large amount of space
 Memory extension will become impossible
 Development of larger memory units SIMM(Single Inline Memory Modules),
DIMM (Dual Inline Memory Modules)
 These modules are assembly of several DRAM chips on a separate board not on
mother board
 This can be plugged to mother board
 SIMMs and DIMMs of diff sizes can be plugged to the same mother board
socket
 For ex: 4M*32, 16M*32 DIMMs use 100 pin socket
 Memory extension is possible
 These modules occupy a smaller amount of space on motherboard
 Memory System Considerations:
 Choice of RAM chip depends upon the application and
several factors
 Factors include cost, speed, power dissipation, size
 Static RAMs costlier, faster than Dynamic RAMs
 Static RAMS are used in cache memories
 For main memory Dynamic RAMs are used
 Economic
 Memory Controller:
 Next Slide