12/7/21

Logic Design and Switching Theory Lab

Introduction to VHDL

Engr. Nabeel Khalid Lecturer FOE,UCP

 12/7/21

Defining a Digital Design

 There are several approaches to define a digital

design
 Boolean equations:
 This describe the function of gates and 1-bit storage
elements.
 Each flip-flop or gate requires an equation.
 It is not practical for a design containing thousand of
gates.

Engr. Nabeel Khalid Lecturer FOE,UCP

 12/7/21

Defining a Digital Design

 Schematics
 This uses previously defined designs in hierarchical
fashion.
 this method is graphical and easily understood.
 This method is limited to small designs. It becomes
incomprehensible after 10,000 gates.
 Hardware description language

Engr. Nabeel Khalid Lecturer FOE,UCP

 12/7/21

Introduction to VHDL
 VHDL stands for VHSIC (Very High Speed Integrated
Circuits) Hardware Description Language.
 In the mid-1980’s the U.S. Department of Defense and
the IEEE sponsored the development of this hardware
description language with the goal to develop very high-
speed integrated circuit.
 Other hardware description languages are Verilog and
System Verilog.
 Now these languages have become industry standards for
making application specific integrated circuits (ASICs).
Engr. Nabeel Khalid
Lecturer
FOE,UCP
 12/7/21

Introduction to VHDL
 These languages look similar as conventional
programming languages, there are some important
differences.
 A hardware description language is inherently parallel, i.e.
commands, which correspond to logic gates, are executed
(computed) in parallel, as soon as a new input arrives.
While the other programming languages are sequential
languages like C,C++.

Engr. Nabeel Khalid

Lecturer
FOE,UCP
 12/7/21

Why VHDL is used?

 Design representation and entry
 Design documentation
 Design simulation
 Design synthesis
 Design verification
 Describe adesign using different abstraction
representations

Engr. Nabeel Khalid

Lecturer
FOE,UCP
 12/7/21

Why VHDL is used?

 High-level programming languages are sequential in
nature.
 Time is not embedded in other high-level languages. It is
hard simulate delays.
 Hardware is parallel in nature.
 VHDL is event driven by design. This speeds simulations.

Engr. Nabeel Khalid

Lecturer
FOE,UCP
 12/7/21

Hardware Description
 VHDL deals with a given component from two point of
views
 External view of the component as seen by the others.
 Multiple internal views describing component function.
• One view might describe the structure of the design
• Another view might describe the function of the design.

Engr. Nabeel Khalid

Lecturer
FOE,UCP
 12/7/21

Digital System
 A digital system can be represented at different levels of
abstraction. This keeps the description and design of
complex systems manageable. The figure below shows
different levels of abstraction.

Engr. Nabeel Khalid

Lecturer
FOE,UCP
 12/7/21

Modeling a Digital system

 There are different modeling styles for a digital system.
1. As a set of interconnected components (structural
modeling)
2. As a set of concurrent assignment statements (dataflow
modeling)
3. As a set of sequential assignment statements (behavioral
modeling)
4. As any combination of the above three (mixed style
modeling)

Engr. Nabeel Khalid

Lecturer
FOE,UCP
 12/7/21

Structural Level
 The structural level, on the other hand, describes a
system as a collection of gates and components that are
interconnected to perform a desired function.
 A structural description could be compared to a
schematic of interconnected logic gates. It is a
representation that is usually closer to the physical
realization of a system.
 For example, an XOR gate is the combination of ‘AND’ and
‘OR’ gates, so it will represented by the combination of
these gates.
Engr. Nabeel Khalid
Lecturer
FOE,UCP
 12/7/21

Behavioral Modeling
 The highest level of abstraction is the behavioral level
that describes a system in terms of what it does (or how it
behaves) rather than in terms of its components and
interconnection between them.
 A behavioral description specifies the relationship
between the input and output signals.
For example
An ‘OR’ gate has a behavior of an Adder, So, its behavior will
be represented by sum function.
Z=X+Y
Engr. Nabeel Khalid
Lecturer
FOE,UCP
 12/7/21

Structure of VHDL code

 A digital system in VHDL consists of a design entity that
can contain other entities that are then considered
components of the top-level entity. Each entity is
modeled by an entity declaration and an architecture
body.
 Structure or behavior of entity is described in side
architecture of entity.
 In a typical design there will be many such entities
connected together to perform the desired function.

Engr. Nabeel Khalid

Lecturer
FOE,UCP
 12/7/21

Structure of VHDL code

 A VHDL entity consisting of an interface (entity
declaration) and a body (architectural description).

Engr. Nabeel Khalid

Lecturer
FOE,UCP
 12/7/21

Structure of VHDL code

 VHDL uses reserved keywords that cannot be used as
signal names or identifiers. VHDL is not a case sensitive
language.
 Lines with comments start with two adjacent hyphens (- -)
and will be ignored by the compiler, VHDL also ignores line
breaks and extra spaces.
 VHDL is a strongly typed language which implies that one
has always to declare the type of every object that can
have a value, such as signals, constants and variables.

Engr. Nabeel Khalid

Lecturer
FOE,UCP
 12/7/21

Entity Declaration
 The entity declaration defines the NAME of the entity and
lists the input and output ports. The general form is as
follows,

entity entity_name is
port (signal_names: mode type;
signal_names: mode type;
:
signal_names: mode type);
end [entity_name ] ;
Engr. Nabeel Khalid
Lecturer
FOE,UCP
 12/7/21

Entity Declaration
 The entity declaration defines the NAME of the entity and
lists the input and output ports. The general form is as
follows,

entity entity_name is
port (signal_names: mode type;
signal_names: mode type;
:
signal_names: mode type);
end [entity_name ] ;
Engr. Nabeel Khalid
Lecturer
FOE,UCP
 12/7/21

Entity Declaration
 mode: is one of the following reserved words to indicate the
signal direction:

 in– indicates that the signal is an input.

 out – indicates that the signal is an output of the entity
whose value can only be read by other entities that use it.
 buffer – indicates that the signal is an output of the entity
whose value can be read inside the entity’s architecture.
 inout – the signal can be an input or an output.

Engr. Nabeel Khalid

Lecturer
FOE,UCP
 12/7/21

Entity Declaration
 type: a built-in or user-defined signal type. Examples of types are
bit, bit_vector, Boolean, character, std_logic, and stc_ulogic.

 bit – can have the value 0 and 1

 bit_vector – is a vector of bit values (e.g. bit_vector (0 to 7)
 std_logic, std_ulogic, std_logic_vector, std_ulogic_vector: can
have 9 values to indicate the value and strength of a signal.
Std_ulogic and std_logic are preferred over the bit or bit_vector
types.
 boolean – can have the value TRUE and FALSE
 integer – can have a range of integer values
 real – can have a range of real values
 character – any printing character
 time – to indicate time Engr. Nabeel Khalid
Lecturer
FOE,UCP
 12/7/21

Entity Declaration (Example)

 AnXOR gate entity can be declared as follows:
entity XORGate is
port( in1, in2: in bit;
out1: out bit);
end;

 An4-bit adder entity can be declared as follows:

entity adder is
port( A, B: in bit_vector (3 downto 0);
Cin: in bit;
SUM: out bit_vector (3 downto 0);
Cout: out bit);
Engr. Nabeel Khalid
end adder; Lecturer
FOE,UCP
 12/7/21

Entity Declaration (Example)

AnThe architecture body specifies how the circuit operates and how it is implemented.
As discussed earlier, an entity or circuit can be specified in a variety of ways, such as
behavioral, structural (interconnected components), or a combination of the above.
The architecture body looks as follows:

architecture architecture_name of NAME_OF_ENTITY is

-- Declarations
-- components declarations
-- signal declarations
-- constant declarations
-- function declarations
-- procedure declarations
-- type declarations
:
begin
-- Statements
end architecture_name;
Engr. Nabeel Khalid
Lecturer
FOE,UCP
 12/7/21

Entity Declaration (Example)

AnThe architecture body specifies how the circuit operates and how it is implemented.
As discussed earlier, an entity or circuit can be specified in a variety of ways, such as
behavioral, structural (interconnected components), or a combination of the above.
The architecture body looks as follows:

architecture architecture_name of NAME_OF_ENTITY is

-- Declarations
-- components declarations
-- signal declarations
-- constant declarations
-- function declarations
-- procedure declarations
-- type declarations
:
begin
-- Statements
end architecture_name;
Engr. Nabeel Khalid
Lecturer
FOE,UCP
 12/7/21

Entity Declaration (Example)

An architecture body of the XORGate entity defined earlier is
given below:

architecture behavioral of XORGate is

begin
out1 <= (not in1 and in2) or (not in2 and in1);
end behavioral;

The header line of the architecture body defines the

architecture name, i.e. behavioral, and associates it with the
entity, XOR. The architecture name can be any legal identifier.
The main body of the architecture starts with the keyword
begin.
Engr. Nabeel Khalid
Lecturer
FOE,UCP
 12/7/21

Entity Declaration (Example)

 The architecture body contains a signal assignment. The “
<= ” symbol represents an assignment operator and
assigns the value of the expression on the right to the
signal on the left.

 The architecture body ends with an end keyword

followed optionally by the architecture name.

Engr. Nabeel Khalid

Lecturer
FOE,UCP
 12/7/21

Test Bench
 Itis module in VHDL which helps to check the behavior of
the VHDL entity.
 In writing test bench code in VHDL, we follow same rules
which are followed for writing code for an entity.
 In test bench, different simulation condition are provided
in the form of code.
 Against these conditions, a specific entity is being tested.

Engr. Nabeel Khalid

Lecturer
FOE,UCP
 12/7/21

Any Questions……..

Engr. Nabeel Khalid

Lecturer
FOE,UCP