What is a computer?

 Simply put, a computer is a

sophisticated electronic calculating
machine that:
 Accepts input information,
 Processes the information according to a
list of internally stored instructions and
 Produces the resulting output information.
 Functions performed by a computer
are: 2
 Functional units of a computer
Input unit accepts Arithmetic and logic unit(ALU):
information: •Performs the desired
•Human operators, operations on the input
•Electromechanical devices information as determined
•Other computers by instructions in the memory

Memory Arithmetic
Input Instr1 & Logic
Instr2
Instr3
Data1
Output Data2 Control

I/O Stores Processor

information: Control unit coordinates
Output unit sends various actions
results of processing: •Instructions,
•Data •Input,
•To a monitor display, •Output
•To a printer •Processing

3
Information in a computer --
Instructions
 Instructions specify commands to:
 Transfer information within a computer (e.g., from memory to ALU)
 Transfer of information between the computer and I/O devices
(e.g., from keyboard to computer, or computer to printer)
 Perform arithmetic and logic operations (e.g., Add two numbers,
Perform a logical AND).

 A sequence of instructions to perform a

task is called a program, which is stored
in the memory.
 Processor fetches instructions that
make up a program4 from the memory
Information in a computer --
Data
 Data are the “operands” upon which
instructions operate.
 Data could be:
 Numbers,

 Encoded characters.

 Data, in a broad sense means any

digital information.
 Computers use data that is encoded as
a string of binary digits
5
called bits.
 Input unit
Binary information must be presented to a computer in a specific format. This
task is performed by the input unit:
- Interfaces with input devices.
- Accepts binary information from the input devices.
- Presents this binary information in a format expected by the computer.
- Transfers this information to the memory or processor.
Real world Computer

Memory

Keyboard
Audio input
Input Unit
……

Processor

6
 Memory unit
 Memory unit stores instructions and data.
 Recall, data is represented as a series of bits.

 To store data, memory unit thus stores bits.

 Processor reads instructions and reads/writes

data from/to the memory during the
execution of a program.
 In theory, instructions and data could be fetched one bit at a time.
 In practice, a group of bits is fetched at a time.
 Group of bits stored or retrieved at a time is termed as “word”
 Number of bits in a word is termed as the “word length” of a computer.

 In order to read/write to and from memory, a

processor should know where to look:
 “Address” is associated with each word location.

7
 Memory unit (contd..)
 Processor reads/writes to/from memory
based on the memory address:
 Access any word location in a short and fixed amount of time based on the
address.
 Random Access Memory (RAM) provides fixed access time independent of
the location of the word.
 Access time is known as “Memory Access Time”.

 Memory and processor have to

“communicate” with each other in order to
read/write information.
 In order to reduce “communication time”, a small amount of RAM (known
as Cache) is tightly coupled with the processor.
 Modern computers have three to four levels of RAM units with different speeds
and sizes:
 Fastest, smallest known as Cache
 Slowest, largest known as Main memory.
8
Memory unit (contd..)
 Primary storage of the computer consists of
RAM units.
 Fastest, smallest unit is Cache.
 Slowest, largest unit is Main Memory.

 Primary storage is insufficient to store large

amounts of data and programs.
 Primary storage can be added, but it is expensive.

 Store large amounts of data on secondary

storage devices:
 Magnetic disks and tapes,
 Optical disks (CD-ROMS).
 Access to the data stored in secondary storage in slower, but take
advantage of the fact that some information may be accessed infrequently.

 Cost of a memory unit depends on its access

time, lesser access time
9 implies higher cost.
Arithmetic and logic unit (ALU)
 Operations are executed in the Arithmetic and
Logic Unit (ALU).
 Arithmetic operations such as addition, subtraction.

 Logic operations such as comparison of numbers.

 In order to execute an instruction, operands

need to be brought into the ALU from the
memory.
 Operands are stored in general purpose registers available in the ALU.

 Access times of general purpose registers are faster than the cache.

 Results of the operations are stored back in

the memory or retained in the processor for
immediate use. 10
 Output unit
•Computers represent information in a specific binary form. Output units:
- Interface with output devices.
- Accept processed results provided by the computer in specific binary form.
- Convert the information in binary form to a form understood by an
output device.

Computer Real world

Memory Printer
Graphics display
Speakers
……
Output Unit

Processor

11
Control unit
 Operation of a computer can be summarized
as:
 Accepts information from the input units (Input unit).
 Stores the information (Memory).
 Processes the information (ALU).
 Provides processed results through the output units (Output unit).

 Operations of Input unit, Memory, ALU and

Output unit are coordinated by Control unit.
 Instructions control “what” operations take
place (e.g. data transfer, processing).
 Control unit generates timing signals which
determines “when” a particular operation
takes place.
12
 How are the functional units
connected?
•For a computer to achieve its operation, the functional units need to
communicate with each other.
•In order to communicate, they need to be connected.

Input Output Memory Processor

Bus

•Functional units may be connected by a group of parallel wires.

•The group of parallel wires is called a bus.
•Each wire in a bus can transfer one bit of information.
•The number of parallel wires in a bus is equal to the word length of
a computer

13
Organization of cache and
main memory
Main Cache
memory memory Processor

Bus

Why is the access time of the cache memory lesser than the
access time of the main memory?

14
 Definition of Terms
ACL: Access Control List
APDIP: Asia Pacific Development Information Programme
APNIC: Asia Pacific Network Information Center
APRICOT: Asia Pacific Regional Internet Conference on
Operational Technologies
BIND: Berkeley Internet Name Domain
CCTLD: Country Code Top Level DOMAIN
CIDR: Classless Inter-Domain Routing
DNS: Domain Name System
DoS: Denial of Service
FOSS: Free/Open Source Software
FQDN: Fully Qualified Domain Name
FTP: File Transfer Protocol
gTLD: Global Top Level Domain
ICANN: Internet Corporation for Assigned Name and Numbers
IDS: Intrusion Detection System
 Definition of Terms
IETF: Internet Engineering Task Force
IOSN: International Open Source Network
IP: Internet Protocol
ISP: Internet Service Provider
LAN: Local Area Network
MTA: Mail Transfer Agent
NAT: Network Address Translation
NetBEUI: NetBIOS Extended User Interface
NIC: Network Interface Card
NOS: Network Operating System
OS: operating system
PCH: Packet Clearing House
POP: Post Office Protocol
RBL: Realtime Block List
RFC: Request for Comments
 Definition of Terms
RIR: Regional Internet Registry
SMTP: Simple Mail Transfer Protocol
SSL: Secure Sockets Layer
TCP: Transmission Control Protocol
UCE: unsolicited commercial e-mail
UDP: User Datagram Protocol
VLAN: Virtual Local Area Network
VPN: Virtual Private Network
WAN: Wide Area Network
Wi-Fi: Wireless Fidelity
WLAN: Wireless Local Area Network
Mano’s Computer Figure 5-4 s0 s1 s2
Bus
Memory Unit
7
4096x16
Address
WRITE READ
AR 1
LD INR CLR
PC 2
LD INR CLR
DR 3
LD INR CLR

Adder E
& Logic
AC 4
LD INR CLR

INPR

IR 5
LD
TR 6
LD INR CLR
OUTR
Clock
LD
16-bit common bus
Computer System Architecture, Mano, Copyright (C) 1993 Prentice-Hall, Inc.
 Computer Registers
–Accumulator(AC) : takes input from ALU
»The ALU takes input from DR, AC and INPR :
»ADD DR to AC, AND DR to AC
–Note) Input register is not connected to the bus.
–The input register is connected only to the ALU
 5-2 Computer Registers
• Data Register(DR) : hold the operand(Data) read from memory

• Accumulator Register(AC) : general purpose processing register

• Instruction Register(IR) : hold the instruction read from memory

• Temporary Register(TR) : hold a temporary data during processing

• Address Register(AR) : hold a memory address, 12 bit width

 5-2 Computer Registers
• Program Counter(PC) :
• hold the address of the next instruction to be read from
memory after the current instruction is executed
• Instruction words are read and executed in sequence unless
a branch instruction is encountered
• A branch instruction calls for a transfer to a nonconsecutive
instruction in the program
• The address part of a branch instruction is transferred to PC
to become the address of the next instruction
• To read instruction, memory read cycle is initiated, and PC is
incremented by one(next instruction fetch)
 IR and TR
• The instruction register, IR, can only be loaded;
it cannot be incremented nor cleared. Its output
is used to generate Di’s and Ti’s control signals.
• TR is a temporary register. The CPU uses this
register to store intermediate results of
operations. It is not accessible by the external
programs. It is loaded, incremented and cleared
like the other registers.
 5-2 Computer Registers

Register Number Register Register

symbol of bits name Function-----------------------
DR 16 Data register Holds memory operands
AR 12 Address register Holds address for memory
AC 16 Accumulator Processor register
IR 16 Instruction register Holds instruction code
PC 12 Program counter Holds address of instruction
TR 16 Temporary register Holds temporary data
INPR 8 Input register Holds input character
OUTR 8 Output register Holds output character
Mano’s Computer Figure 5-4 s0 s1 s2
Bus
Memory Unit
7
4096x16
Address
WRITE READ
AR 1
LD INR CLR
PC 2
LD INR CLR
DR 3
LD INR CLR

Adder E
& Logic
AC 4
LD INR CLR

INPR

IR 5
LD
TR 6
LD INR CLR
OUTR
Clock
LD
16-bit common bus
Computer System Architecture, Mano, Copyright (C) 1993 Prentice-Hall, Inc.
Common Bus System
 The basic computer has eight registers, a
memory unit, and a control unit.

 Paths must be provided to transfer

information from one register to another and
between memory and registers

 A more efficient scheme for transferring

information in a system with many registers
is to use a common bus.
Common Bus System
 The connection of the registers and memory of
the basic computer to a common bus system :

 The outputs of seven registers and memory are connected

to the common bus
 The specific output is selected by mux(S0, S1, S2) :
 Memory(7), AR(1), PC(2), DR(3), AC(4), IR(5), TR(6)

 When LD(Load Input) is enable, the particular register

receives the data from the bus

 Control Input : LD, INC, CLR, Write, Read
COMMON BUS SYSTEM
 Control variables: the bus is
controlled by

 1- Selection switches for selecting the

source of information and
 2- Enable switches at the destination
device to accept the information.
Selection variables
 Selection variables: select a register or the
memory whose output is used as an input to
the common bus.

 To select one device out of 8, we need 3

select variables.
 For example, if S2S1S0 = 011, the output of
DR is selected as an output of the common
bus.
 Load input
Load input (LD): Enables the input of a
register to download bits form the
common bus. When LD = 1 for a
register, the data on the common bus is
read into the register during the next
clock pulse transition.

> Increment input (INR): Increments the content of a register.

> Clear input (CLR): Clear the content of a register to zero.
Incompatibility in register sizes

 • When the contents of AR or PC (12 bits) are

applied to the 16-bit common bus, the four
most significant bits are set to zero. When AR
or PC receives information from the bus, only
the 12 least significant bits are transferred to
the register.
12 least significant bits

12 bits
Instruction Codes
A process is controlled by a program
 A program is a set of instructions that
specify the operations, data, and the
control sequence
 An instruction is stored in binary code that
specifies a sequence of microoperations
 Instruction codes together with data are
stored in memory (Stored Program
Concept)
 Building A Basic Computer!
The basic computer instructions are
1. Memory
stored in the memory
address contents
The size of each memory word is 16 bits.
Each instruction occupy one word. 000000000001 0101010101010101
000000000010 1010101010101010
000000000011 1100110011001100
2. Program Counter
000000000100 0011001100110011
PC 000000000001 000000000101 0101010101010011
000000000110 1010101010101010
000000000111 1100110011001100

3. Instruction Register 000000001000 0011001100110011

IR 0101010101010101
 The address register is connected to the
memory
+1
The Program Counter points to PC
the next address of the program
000000000010
00000001

1. Program Counter Increments

by units of addresses AR 000000000010
2. The next address is put on
the bus and is loaded into the
Direct access to
Address Register
Memory
3. The Bits of the AR are wired
directly to the RAM Address
lines to enable loading the
memory into the Instruction R. IR 1010101010101010
Program statements and
computer instructions

Computer
instruction

Field specifying the Field specifying the

operation to be data
executed To be operated on
Instruction code format
 Instruction code format with two parts :
Op. Code + Address
 Op. Code : specify 16 possible operations(4 bits)
 Address : specify the address of an operand(12
bits)
 If an operation in an instruction code does not
need an operand from memory, the rest of the
bits in the instruction (address field) can be used
for other purpose
15 12 11 0 15 12 11 0

Op. Code Address data

instruction Not an instruction

 Instructions are read from memory as
words

 Instructions can be formatted to fit in one or

more memory words.
 An instruction may contain
 An opcode + data (immediate operand)
 An opcode + the address of data (direct addressing)
 An opcode + an address where the address of the data
is found (indirect addressing)
 Data only (location has no instructions)
 An opcode only (register-reference or input/output
instruction)
Direct address
Occurs When the Operand Part Contains the Address of
Needed Data.

1. Address part of IR is placed on the bus and loaded

back into the AR

2. Address is selected in memory and its Data placed on

the bus to be loaded into the Data Register to be used for
requested instructions
Mano’s Computer Figure 5-4 s0 s1 s2
Bus
Memory Unit
7
4096x16
Address
WRITE READ
AR 1
LD INR CLR
PC 2
LD INR CLR
DR 3
LD INR CLR

Adder E
& Logic
AC 4
LD INR CLR

INPR

IR 5
LD
TR 6
LD INR CLR
OUTR
Clock
LD
16-bit common bus
Computer System Architecture, Mano, Copyright (C) 1993 Prentice-Hall, Inc.
Direct address
Indirect address
Occurs When the Operand Contains the Address of the Address
of Needed Data.

1. Address part of IR is placed on the bus and loaded back

into the AR

2. Address is selected in memory and placed on the bus to be

loaded Back into the AR

3. New Address is selected in memory and placed on the bus

to be loaded into the DR to use later
Indirect address
Effective address:
• Effective address: Address where an
operand is physically located

Effective address: 457 Effective address: 1350

 Mano’s Computer: each instruction
occupies one Memory Words
15 12 11 0

• 4-bit opcode Bits 15-12

• How many possible instructions?
– 24=16
• This leaves 12 bits for the address
– How many words of memory?
– 212 = 22•210 = 4K = 4096 16-bit words
 Mano's simple Computer:
Instructions 0
15 12 11

Any bits other than 0111 and

I 1111 are called memory reference
instructions
000 AND 100 BUN
001 ADD (Branch Unconditional)
010 LDA 101 BSA
(Load Accumulator) (Branch and Store Address)
011 STA 110 ISZ
(Store Accumulator) (Increment and Skip if Zero)
 5-3. Computer Instruction
•
– 3 Instruction Code Formats : Fig. 5-5 Hex Code
Symbol I=0 I=1 Description
• Memory-reference instruction AND 0xxx 8xxx And memory word to AC
ADD 1xxx 9xxx Add memory word to AC
–Opcode = 000  110 LDA 2xxx Axxx Load memory word to AC
STA 3xxx Bxxx Store content of AC in memory
»I=0 : 0xxx ~ 6xxx, I=1: 8xxx ~Exxx BUN 4xxx Cxxx Branch unconditionally
I=0 : Direct, 15 14 12 11 0 BSA 5xxx Dxxx Branch and Save return address
I=1 : Indirect ISZ 6xxx Exxx Increment and skip if zero
I Opcode Address CLA 7800 Clear AC
CLE 7400 Clear E
CMS 7200 Complement AC
»Register-reference instruction CME 7100 Complement E
–7xxx (7800 ~ 7001) : CLA, CMA, CIR
CIL
7080
7040
Circulate right AC and E
Circulate left AC and E
15 14 12 11 0 INC 7020 Increment AC
0 1 1 1 Register Operation SPA 7010 Skip next instruction if AC positive
SNA 7008 Skip next instruction if AC negative
SZA 7004 Skip next instruction if AC zero
–Input-Output instruction SZE 7002 Skip next instruction if E is 0
HLT 7001 Halt computer
–Fxxx(F800 ~ F040) : INP, OUT, ION, SKI, INP F800 Input character to AC
OUT F400 Output character from AC
15 14 12 11 0 SKI F200 Skip on input flag
SKO F100 Skip on output flag
1 1 1 1 I/O Operation ION F080 Interrupt On
IOF F040 Interrupt Off
5.5 Instruction Cycle
 A computer goes through the following
instruction cycle repeatedly:
do
1. Fetch an instruction from memory
2. Decode the instruction
3. Read the effective address from
memory if the instruction has an
indirect address
4. Execute the instruction until a HALT
instruction is encountered
Precision Time Protocol
(PTP)
The Precision Time Protocol, as defined in the IEEE-
1588 standard, provides a method to precisely
synchronize computers over a Local Area Network (LAN)
to an accuracy that was previously unobtainable. On an
existing LAN, PTP is capable of synchronizing multiple
clocks to better than 10 microseconds RMS. A Network
Time Server with a GPS or CDMA receiver and PTP is
typically referred to as an “IEEE-1588 GrandMaster”. This
paper will describe the basic principles of PTP, various
implementations of PTP, measurement methods, and
synchronization results using an EndRun GrandMaster.
Mano’s Computer Figure 5-4 s0 s1 s2
Bus
Memory Unit
7
4096x16
Address
WRITE READ
AR 1
LD INR CLR
PC 2
LD INR CLR
DR 3
LD INR CLR

Adder E
& Logic
AC 4
LD INR CLR

INPR

IR 5
LD
TR 6
LD INR CLR
OUTR
Clock
LD
16-bit common bus
Computer System Architecture, Mano, Copyright (C) 1993 Prentice-Hall, Inc.
 Quiz 1 Finals

A Computer instruction may contain

1. An opcode + data (immediate operand)
2. An opcode + the address of data (direct addressing)
3. An opcode + an address where the address of the data
is found (indirect addressing)
4. Data only (location has no instructions)
5. An opcode only (register-reference or input/output
instruction)
Computer Registers:
• Data Register(DR) : hold the operand(Data) read from memory
• Accumulator Register(AC) : general purpose processing register
• Instruction Register(IR) : hold the instruction read from memory
• Temporary Register(TR) : hold a temporary data during processing
• Address Register(AR) : hold a memory address, 12 bit width
 T0:Address transfer between PC and AR
T0: Since only AR is connected to the address inputs of memory,
the address of instruction is transferred from PC to AR.
1. Place the content of PC onto the bus by making the bus
selection inputs S2S1S0 = 010.
2. Transfer the content of the bus to AR by enabling the LD input
of AR ( AR PC).
 T1: Data transfer between Memory and IR
T1: The instruction read from memory is
placed in IR. At the same time, PC is
incremented to the address of the next
instruction.
1. Enable ‘read input’ of the memory.
2. Place the content of memory onto the
bus using the bus selection inputs
S2S1S0 = 111. (Note that the address
lines are always connected to AR, and
the next instruction address has been
already placed in AR.)
3. Transfer the content of the bus to IR
by enabling LD input to IR
(IR M[AR]).
4. Increment PC by enabling the INR
input of PC ( PC PC + 1 ).
 Decoding at T2
T2: The operation code in IR is
decoded; the indirect bit is
transferred to I; the address
part of the instruction is
transferred to AR.
 Instruction Cycle
• At T3, microoperations which take place depend
on the type of instruction. The four different
paths are symbolized as follows,

Control function Microoperation

D7`IT3: AR M[AR], indirect memory
transfer
D7`I`T3: Nothing, direct memory
transfer
D7I`T3: Execute a register-reference
instruction
D7IT3: Execute an I/O
instruction
 5-3. Computer Instruction
•
– 3 Instruction Code Formats : Fig. 5-5 Hex Code
Symbol I=0 I=1 Description
• Memory-reference instruction AND 0xxx 8xxx And memory word to AC
ADD 1xxx 9xxx Add memory word to AC
–Opcode = 000  110 LDA 2xxx Axxx Load memory word to AC
STA 3xxx Bxxx Store content of AC in memory
»I=0 : 0xxx ~ 6xxx, I=1: 8xxx ~Exxx BUN 4xxx Cxxx Branch unconditionally
I=0 : Direct, 15 14 12 11 0 BSA 5xxx Dxxx Branch and Save return address
I=1 : Indirect ISZ 6xxx Exxx Increment and skip if zero
I Opcode Address CLA 7800 Clear AC
CLE 7400 Clear E
CMS 7200 Complement AC
»Register-reference instruction CME 7100 Complement E
–7xxx (7800 ~ 7001) : CLA, CMA, CIR
CIL
7080
7040
Circulate right AC and E
Circulate left AC and E
15 14 12 11 0 INC 7020 Increment AC
0 1 1 1 Register Operation SPA 7010 Skip next instruction if AC positive
SNA 7008 Skip next instruction if AC negative
SZA 7004 Skip next instruction if AC zero
–Input-Output instruction SZE 7002 Skip next instruction if E is 0
HLT 7001 Halt computer
–Fxxx(F800 ~ F040) : INP, OUT, ION, SKI, INP F800 Input character to AC
OUT F400 Output character from AC
15 14 12 11 0 SKI F200 Skip on input flag
SKO F100 Skip on output flag
1 1 1 1 I/O Operation ION F080 Interrupt On
IOF F040 Interrupt Off
For example
 7040 (in hexadecimal)., In binary this is
equivalent to: 0111 0000 0100 0000 (CIL)
Register Transfer Statement IR AC DR PC AR M[AR] E
Initial Values 1200 0001 00C7 035 200 0400 0
T0: AR  PC ---- ---- ---- ---- 035 7040 ----
T1: IR  M[AR] , 7040 ---- ---- 036 ---- ---- ----
PC  PC+1
T2: AR  IR(0-11) ---- ---- ---- ---- 040 0400 ----
T3 ---- 0002 ---- ---- ---- ---- 0

---- : means the same with previous value

For example
 7080 (in hexadecimal)., In binary this is
equivalent to: 0111 0000 1000 0000
(CIR)
Register Transfer Statement IR AC DR PC AR M[AR] E
Initial Values 1200 0001 00C7 035 200 0400 0
T0: AR  PC ---- ---- ---- ---- 035 7080 ----
T1: IR  M[AR] , 7080 ---- ---- 036 ---- ---- ----
PC  PC+1
T2: AR  IR(0-11) ---- ---- ---- ---- 080 unknow ----
T3 ---- 8000 ---- ---- ---- ---- 1

---- : means the same with previous value

For example
 7100 (in hexadecimal)., In binary this is
equivalent to: 0111 0001 0000 0000
(Complement E)
 7010 (Bi=bit in position i =4) in binary
0111 0000 0001 0000 (skip if positive)
Mano's Computer: RTL ACTIONS in T3
 5-3. Computer Instruction
•
– 3 Instruction Code Formats : Fig. 5-5 Hex Code
Symbol I=0 I=1 Description
• Memory-reference instruction AND 0xxx 8xxx And memory word to AC
ADD 1xxx 9xxx Add memory word to AC
–Opcode = 000  110 LDA 2xxx Axxx Load memory word to AC
STA 3xxx Bxxx Store content of AC in memory
»I=0 : 0xxx ~ 6xxx, I=1: 8xxx ~Exxx BUN 4xxx Cxxx Branch unconditionally
I=0 : Direct, 15 14 12 11 0 BSA 5xxx Dxxx Branch and Save return address
I=1 : Indirect ISZ 6xxx Exxx Increment and skip if zero
I Opcode Address CLA 7800 Clear AC
CLE 7400 Clear E
CMS 7200 Complement AC
»Register-reference instruction CME 7100 Complement E
–7xxx (7800 ~ 7001) : CLA, CMA, CIR
CIL
7080
7040
Circulate right AC and E
Circulate left AC and E
15 14 12 11 0 INC 7020 Increment AC
0 1 1 1 Register Operation SPA 7010 Skip next instruction if AC positive
SNA 7008 Skip next instruction if AC negative
SZA 7004 Skip next instruction if AC zero
–Input-Output instruction SZE 7002 Skip next instruction if E is 0
HLT 7001 Halt computer
–Fxxx(F800 ~ F040) : INP, OUT, ION, SKI, INP F800 Input character to AC
OUT F400 Output character from AC
15 14 12 11 0 SKI F200 Skip on input flag
SKO F100 Skip on output flag
1 1 1 1 I/O Operation ION F080 Interrupt On
IOF F040 Interrupt Off
5.6 Memory Reference Instructions
• Opcode (000 - 110) or the decoded output Di (i = 0, ..., 6) are used
to select one memory-reference operation out of 7.
Memory Reference
Instructions
 Since the data stored in memory cannot be
processed directly (the memory unit is not
connected to the ALU), the actual execution
in the bus system require a sequence of
microoperations.

 (Note that T0-T2 for fetch an instruction; T3

for AR  M[AR] if indirect memory
addressing.
 Computer Registers
–Accumulator(AC) : takes input from ALU
»The ALU takes input from DR, AC and INPR :
»ADD DR to AC, AND DR to AC
–Note) Input register is not connected to the bus.
–The input register is connected only to the ALU
AND to AC
 AND to AC: Logical AND operation between AC and
the memory word specified by AR.
 (Note that T0-T2 for fetch an instruction; T3 for AR
 M[AR] if indirect memory addressing.

 Need 2 more cycles for the AND logical operation

since only DR is connected to ALU.)
 D0T4: DR  M[AR]
 D0T5: AC  AC ˆ DR, SC  0
 SC – start counter
Register Transfer Statement IR AC DR PC AR M[AR] E
Initial Values 1200 8000 00C7 036 080 unknow 1
T0: AR  PC ---- ---- ---- ---- 036 0200 ----
T1: IR  M[AR] , 0200 ---- ---- 037 ---- ---- ----
PC  PC+1
T2: AR  IR(0-11) ---- ---- ---- ---- 200 0400 ----
T3: ---- ---- ---- ---- ---- ---- ----
T4: ---- ---- 0400 ---- ---- ---- ----
T5: ---- 0000 ---- ---- ---- ---- ----

---- : means the same with previous value

Register Transfer Statement IR AC DR PC AR M[AR] E
Initial Values 1200 8000 00C7 035 080 unkno 1
w
T0: AR  PC ---- ---- ---- ---- 035 8200 ----
T1: IR  M[AR] , 8200 ---- ---- 036 ---- ---- ----
PC  PC+1
T2: AR  IR(0-11) ---- ---- ---- ---- 200 0400 ----
T3: ---- ---- ---- ---- 400 0000 ----
T4: ---- ---- 0000 ---- ---- ---- ----
T5: ---- 0000 ---- ---- ---- ---- ----

---- : means the same with previous value

ADD to AC
 ADD to AC: Arithmetic addition
operation between AC and the memory
word specified by AR.
 D1T4: DR  M[AR]
 D1T5: AC  AC + DR, SC  0
Load to AC
 LDA: Load to AC.
 (Need 2 cycles since AC input is not
connected to the bus.)

 D2T4: DR  M[AR]
 D2T5: AC  DR, SC  0
Store AC
 STA: Store AC.
 D3T4: M[AR]  AC, SC  0
Branch unconditionally
 BUN: Branch unconditionally. Transfers
the program to the instruction specified
by AR. (Note that the branch target
must be in AR beforehand.)

 D4T4: PC  AR, SC  0
Branch and save return
address
 This instruction is useful for branching
to a position of the program called a
subprogram

 BSA: Branch and save return address.

Branch to address AR and save PC address.
 • BSA is used to implement a subroutine call.
The indirect BUN instruction at the end of the
subroutine performs the subroutine return.
Branch and save return
address
 Note that the above microoperations
require 2 cycles.
 D5T4: M[AR]  PC, AR  AR + 1
(increment, INR AR)

 D5T5: PC  AR, SC  0
Increment and skip if zero
 ISZ: Increment and skip if zero.

 Programmer usually stores a negative

number in the memory word (in two’s
complement form).
 As this negative number is repeatedly
incremented by one, it eventually reaches
zero. At that time PC is incremented by one
in order to skip the next instruction.
Increment and skip if zero
 increment: M[AR] M[AR] + 1, if (M[AR]
+ 1 = 0) then PC  PC + 1

 increment and skip if zero requires 3 cycles.

 D6T4: DR  M[AR]
 D6T5: DR  DR + 1
 D6T6: M[AR]  DR, if DR=0 then
PC  PC + 1, SC  0
 5-3. Computer Instruction
•
– 3 Instruction Code Formats : Fig. 5-5 Hex Code
Symbol I=0 I=1 Description
• Memory-reference instruction AND 0xxx 8xxx And memory word to AC
ADD 1xxx 9xxx Add memory word to AC
–Opcode = 000  110 LDA 2xxx Axxx Load memory word to AC
STA 3xxx Bxxx Store content of AC in memory
»I=0 : 0xxx ~ 6xxx, I=1: 8xxx ~Exxx BUN 4xxx Cxxx Branch unconditionally
I=0 : Direct, 15 14 12 11 0 BSA 5xxx Dxxx Branch and Save return address
I=1 : Indirect ISZ 6xxx Exxx Increment and skip if zero
I Opcode Address CLA 7800 Clear AC
CLE 7400 Clear E
CMS 7200 Complement AC
»Register-reference instruction CME 7100 Complement E
–7xxx (7800 ~ 7001) : CLA, CMA, CIR
CIL
7080
7040
Circulate right AC and E
Circulate left AC and E
15 14 12 11 0 INC 7020 Increment AC
0 1 1 1 Register Operation SPA 7010 Skip next instruction if AC positive
SNA 7008 Skip next instruction if AC negative
SZA 7004 Skip next instruction if AC zero
–Input-Output instruction SZE 7002 Skip next instruction if E is 0
HLT 7001 Halt computer
–Fxxx(F800 ~ F040) : INP, OUT, ION, SKI, INP F800 Input character to AC
OUT F400 Output character from AC
15 14 12 11 0 SKI F200 Skip on input flag
SKO F100 Skip on output flag
1 1 1 1 I/O Operation ION F080 Interrupt On
IOF F040 Interrupt Off
Mano's Computer: RTL ACTIONS in T3
5.7 IO and Interrupt
 Input-Output Configuration :

 Input Register(INPR), Output Register(OUTR)

 These two registers communicate with a

communication interface serially and with the
AC in parallel
 Each quantity of information has eight bits of
an alphanumeric code
IO and Interrupt
 Input Flag(FGI), Output Flag(FGO)

 FGI : set when INPR has information,

clear when INPR is empty

 FGO : set when operation is completed,

clear when output device is active (for
example a printer is in the process of
printing)
IO instructions
 These instructions are executed with
the clock transition associated with
timing signal T3
 For these instructions, D7=1 and I=1
 The control function is distinguished by
one of the bits in IR(6-11)
Program Interrupt
 Program Interrupt
 Two I/O Transfer Modes

 1) Programmed I/O

 2) Interrupt-initiated I/O (FGI FGO)

 IEN: interrupt enable flip-flop

 R: interrupt flip-flop
 T0'T1'T2' ( IEN )( FGI  FGO) : R  1
Instruction cycle =0 =1 Interrupt cycle
R

Fetch and decode

Store return address
instruction
in location 0
M[0] PC

=0
Execute IEN
instruction
=1
Branch to location 1
PC 1
=1
FGI

=0

=1 IEN 0
FGO R 0

=0

R 1
 Program Interrupt
 Demonstration of the interrupt cycle :
 The memory location at address 0 is the

place for storing the return address

 Interrupt Branch to memory location 1

 Interrupt cycle IEN=0

0 256(return address)
PC = 1 0 BUN 1120
Main Program
Interrupt 255
Here 256

Save Return RT0 : AR  0, TR  PC 1120 Interrupt

Address(PC) at 0 Service Routine
RT1 : M [ AR]  TR, PC  0
Jump to 1(PC=1) 1 BUN 0
RT2 : PC  PC  1, IEN  0, R  0, SC  0
Mano's Computer: RTL