Reconfigurable Computing

ES ZG554
Session 1
Pawan Sharma
BITS Pilani [email protected]
Pilani Campus 04/08/2018
Today’s Lecture

• Course Overview
• Module: Introduction to Reconfigurable
Computing
– General Purpose Computing [T1. Sec 1]
– Domain and Application specific processors [T1. Sec 2
& 3]
– Reconfigurable Computing [T1. Sec 4]
– Fields of Application [T1. Sec 5.1 to 5.4]

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Course Overview

• Reconfigurable Computing is emerging as an important new

organizational structure for implementing computations.
• It combines the post-fabrication programmability of processors
with the spatial computational style most commonly employed
in hardware designs.
• The result changes traditional “hardware” and “software”
boundaries, providing an opportunity for greater computational
capacity and density within a programmable media.
• Its key feature is the ability to perform computations in hardware
to increase performance, while retaining much of the flexibility
of a software solution.
• FPGAs blend benefits of both hardware and software

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 Course Modules
Module 1: To understand the basics of reconfigurable computing, general purpose computing, domain
specific and application specific processors.
Introduction to Reconfigurable computing

Module 2: Reconfigurable Computing Present a basic overview of simple programmable devices like ROM, PLA/PAL, SPLD and
Hardware CPLD.

Module 3: Hardware Description Covers the basics of Verilog language, a hardware description language used to simulate the
Languages and Logic design functional behavior of digital designs

Module 4: Reconfigurable Computing To understand the technology as well as the coupling possibilities of reconfigurable systems,
Architecture from the fine-grained look up table (LUT)-based reconfigurable systems like the field
programmable gate arrays (FPGA) to the new coarse-grained technology.

Module 5: Programming Reconfigurable To understand the implementation on reconfigurable system. It covers the steps needed
Systems (design entry, functional simulation, logic synthesis, technology mapping, place and route
and bit stream generation) to implement today’s FPGAs.

Module 6: Mapping designs to Cover the key mapping steps, functional and structural, unique to field-programmable gate
reconfigurable Platform arrays (FPGAs) and reconfigurable targets, include technology mapping to the primitive
FPGA programmable gates, summarizes the key algorithms used to map reconfigurable
designs
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Module 7: High-Level It considers the high-level synthesis for reconfigurable systems, also known as temporal partitioning. It
Synthesis for Reconfigurable covers the implementation of large functions, which cannot fit into one RPU.
Devices

Module 8: Temporal To understand the stand-alone reconfigurable systems and knowing different ways of operating systems
placement and Routing for reconfigurable systems in charge of managing the resources of a given system and allocate space on
a device for the computation of incoming tasks.

Module 9: Online Modules dynamically placed at run-time on a given device need to communicate with each other in
Communication order to exchange data. Therefore, they dynamically create a need of communication channels on the
chip. This module reviews and explains the different approaches to solve this dynamic
intercommunication need.

Module 10: Reconfiguration Understand ways to reduce configuration overhead, reduce configuration time and configuration
Management encryption techniques

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Text and Reference Books

T1 Introduction to Reconfigurable Computing: Architectures, Algorithms and Applications.

Christophe Bobda, Springer, 2007

R1 Wolf Wayne, FPGA Based System Design, Pearson Edu, 2004.

R2 Scott Hauck, André DeHon, Reconfigurable Computing - The Theory and Practice of FPGA
Based Computation, The Morgan Kaufmann Series in Systems on Silicon, 2007.
R3 Verilog HDL, Samir Palnitkar, Prentice Hall, 2003.

R4 R Vaidyanathan, Trahan Jerry, Dynamic Reconfiguration: Architectures and Algorithms, L,

Kluwer Academic, 2003.
R5 Xilinx, Altera and Microsemi Architecture reference manual

R6 Giovanni De Micheli, synthesis and optimization of digital circuits, Tata McGraw-Hill, 2003

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Evaluation Component

No Name Type Duration Weight Day, Date, Session, Time

Lab Assignment-I Online - 10% September 10-20, 2018

EC-1 Lab Assignment-II Online - 10% November 10-20, 2018

EC-2 Mid-Semester Test Closed Book 2 hours 30% 30/09/2018 (FN) 10 AM – 12 Noon

EC-3 Comprehensive Exam Open Book 3 hours 50% 25/11/2018 (FN) 9 AM – 12 Noon

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Lab Details
• Use of Xilinx Vivado software
• Software and hardware to be accessed from central remote
lab facilities, using Internet
• Need high speed internet connection to access, preferably
>4 Mbps
• If available, you may also use your own copy of software
and hardware
• Assignments to be uploaded on course page within timeline
• Lab access material would be available on course page

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Introduction
Research in computer (processor) architecture
The investing goals vary according to
• Target applications
• Price of the final equipment
• Programmability of the system
• The environment in which processors will be deployed
• Many others

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Computing Paradigms
• The Von Neumann Computer
• Pipelining
• Domain specific processors
• Application Specific Integrated Circuits (ASIC)
• Application specific instruction set processors
• Reconfigurable Processors

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The Von Neumann Computer
• In 1945, the mathematician Von Neumann
(VN) demonstrated in study of computation that a
computer could have a simple structure, capable of
executing any kind of program, given a properly
programmed control unit, without the need of hardware
modification
• Success story of VN computer
• Even till today but losing its dominance
• Simplicity in programming
• Follows sequential way of human thinking

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The Von Neumann Computer
 Structure
o A memory for storing program and data.
• The memory consists of the word with the same length
o A control unit (control path) featuring a program counter for
controlling program execution
o An arithmetic and logic unit (ALU) also called data path for program
execution Processor or
Memory
Central processing unit

Datapath Data

Registers Data
and
Instructions

Instruction Address
register
PC Address
register
Controllpath

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The Von Neumann Computer
 Coding
A program is coded as a set of instructions to be sequentially
executed

 Program execution
– Instruction Fetch (IF): The next instruction to be executed is
fetched from the memory
– Decode (D): The instruction is decoded to determine the
operation
– Read operand (R): The operands are read from the memory
– Execute (EX): The required operation is executed on the ALU
– Write result (W): The result of the operation is written back to the
memory
– Instruction execution in Cycle (IF, D, R, EX,W)

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The Von Neumann Computer
 Advantage:
• Flexibility: any well coded program can be executed
• Control Unit gets data and instruction in the same way from one memory. It simplifies design and
development of the Control Unit.
• Data from memory and from devices are accessed in the same way.
• Memory organization is in the hands of programmers.

 Disadvantages
– Speed efficiency: Not efficient, due to the sequential program execution
(temporal resource sharing).
• Resource efficiency: Only one part of the hardware resources is required for the
execution of an instruction. The rest remains idle.
• One bus is a bottleneck. Only one information can be accessed at the same time.
• Memory access: Memories are about 1000 time slower than the processor
• Instruction stored in the same memory as the data can be accidentally rewritten
by an error in a program.
o Drawbacks are compensated using high clock speed, pipelining,
caches, instruction pre-fetching, etc.
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The Von Neumann Computer
 Sequential execution
 tcycle = cycle execution time
➢ One instruction needs tinstrcution = 5*tcycle
➢
3 instructions are executed in 15*tcycle

 Pipelining:
 One instruction needs tinstrcution = 5*tcycle
o no improvement. In instruction cycle
 3 instructions need 7*tcycle in the ideal
case.
 9*tcycle on a Harvard architecture.

 Increased throughput

 Even with pipeline and other improvements like cache, the execution remain sequential.

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Domain specific processors
 Goal: Overcome the drawback of the von Neumann
computer.
 Optimized Datapath for a given class of applications
 Example: DSP (Digital Signal Processors):
Signal processing applications are usually multiply
accumulate (MAC) dominated.
o Datapath optimized to execute one or many MACs in only one cycle.
o Instruction fetching and decoding overhead is removed
o Memory access is limited by directly processing the input dataflow

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Domain specific processors
 Conclusion
o Faster than VN (MAC in 1 cycle; but for VN 10 steps
required)
o Customised according to the application domain
• If the DSP is for image processing (each pixel 8-bit for RGB);
then it cannot be used again for applications requiring 32-bit
computation

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Application Specific Integrated Circuit
(ASIC)
 Optimize the complete circuit for a given function
o Optimization is done by implementing the inherent parallel structure
on a chip
o The data path is optimized for only one application.
o Instruction fetching and decoding overhead is removed
o Instruction set implemented in hardware
o Memory access is limited by directly processing the input data flow
o Exploitation of parallel computation
o Differs from standard products (ASSP – Application specific standard products)
o ICs that are not ASICs are: DRAM, SRAM
o ASIC examples: baseband processor in mobile phones, chipsets in PCs,
MPEG encoder/decoder, DSP functions

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