Timing

For Pipelined System

BITS Pilani
Pilani Campus
 Synchronization

Well defined ordering of switching events for circuit to

operate correctly
In synchronous system approach---all memory elements
are simultaneously updated using a global clock.
Register based clocking (robust, reliable) , latch based
clocking

12/4/2018 2
BITS Pilani, Pilani Campus
Bit Rate

Most digital signals are aperiodic

Period and frequency are not appropriate to describe

digital signals

Bit Interval - time to send one bit

Bit rate - number of bits sent in a second. Measured in

bits per second bps - Bits Per Second

Do NOT use Hz when you mean bps or vice-versa

CSIS 625 3
Pipelining

• To accelerate the operation of data path,

pipelining is used
• Computation is performed in assembly line
like fashion
• Pipelined network outperforms original
circuit with respect to speed
• Macro pipeline, micro pipeline

12/4/2018 4
Pipeline PCU— MACRO LEVEL

12/4/2018 5
 Pipelined
datapath

MICRO-LEVEL

12/4/2018 6
Timing Parameters
R1 R2
In Combinational
D Q D Q
Logic

CLK tCLK1 tCLK2

tc - q tlogic
tc - q, cd tlogic, cd
tsu, thold

• Assume positive edge triggered system

12/4/2018 7
 Timing Definitions

CLK
t Register
tsu thold D Q

D DATA CLK
STABLE t
tc 2 q

Q DATA
STABLE t

12/4/2018 8
Timing constraint
• Ideal clock

Minimum cycle time:

T > tc-q + tsu + tlogic

Hold time constraint:

thold < t(c-q, cd) + t(logic, cd)

12/4/2018 9
 Clock Non-idealities
• Clock skew
– Spatial variation in arrival time of a clock
transition.
– It is caused by mismatches in clock path or clock
load
– It can be positive or negative depending upon
routing direction and position of clock source
– Clock skew does not result in clock period
variation but only in phase shift

12/4/2018 10
 Positive and Negative Skew
R1 R2 R3
In Combinational Combinational
D Q D Q D Q •••
Logic Logic

CLK tCLK1 tCLK2 tCLK3

delay delay
(a) Positive skew

R1 R2 R3
In Combinational Combinational
D Q D Q D Q •••
Logic Logic

tCLK1 tCLK2 tCLK3

delay delay CLK

(b) Negative skew

12/4/2018 11
 Positive Skew

TCLK + d
TCLK
1 3
CLK1
d

CLK2 2 4
d + th

Launching edge arrives before the receiving edge

12/4/2018 12
 Impact of positive clock skew
R1 R2
In Combinational
D Q D Q
Logic

CLK tCLK1 tCLK2

tc - q tlogic
tc - q, cd tlogic, cd
tsu, thold

Minimum cycle time:

T +  = tc-q + tsu + tlogic
Worst case is when receiving edge arrives early (positive )

12/4/2018 13
Race condition
• Hold time constraint:

• thold +  < t(c-q, cd) + t(logic, cd)

12/4/2018 14
 Negative Skew

TCLK - 
TCLK
1 3
CLK1

CLK2 2 4


Receiving edge arrives before the launching edge

12/4/2018 15
 Impact of negative clock skew
R1 R2
In Combinational
D Q D Q
Logic

CLK tCLK1 tCLK2

tc - q tlogic
tc - q, cd tlogic, cd
tsu, thold

Minimum cycle time:

T -  = tc-q + tsu + tlogic
Worst case is when receiving edge arrives early (positive )

12/4/2018 16
 No Race condition
• Probability of race condition is reduced or
nil
• thold -  < t(c-q, cd) + t(logic, cd)

• System never fails as new data latched

on to R1 never gets transferred to R2 as it
would turn off
12/4/2018 17
Clock Non-idealities
• Clock jitter
– Temporal variations of the clock period at a
given point on the chip. i. e Clock period
reduces or expands on a cycle by cycle basis
– Absolute jitter (tjitter)---worst case variation of a
clock edge at a given location with respect to
an ideal clock.
– Worst case--- Tclk reduces by 2t jitter
– Cycle to cycle jitter (T jitter) ---deviation of
single clock period relative to ideal clock.

12/4/2018 18
 Impact of Jitter---always slows down
 TC LK 
 t j itter
CLK  
-tji tte r 

REGS Combinat ional

In Logi c

CLK t log ic
tc-q , tc-q, cd t log ic, cd
ts u, thold
tjitter

12/4/2018 19
Clock Non-idealities

• Variation of the pulse width

– Important for level sensitive clocking

12/4/2018 20
Combined Impact

12/4/2018 21
Hold time constraint (pos skew)

thold + tjitter +δ - tjitter ≤ tc-q cd + tlogic, cd

•Minimum time available (pos skew)

Tclk +δ - 2tjitter ≥ tc-q + tlogic + t su

Tclk ≥ tc-q + tlogic + t su -δ +2tjitter

12/4/2018 22
 Clock Skew and Jitter
Clk
tSK

Clk tJS

• Both skew and jitter affect the effective cycle time

• Only skew affects race condition (same edge at both
register locations)

12/4/2018 23
Sources of skew and jitter
• Clock signal generation
• Manufacturing device variations
• Interconnect variations
• Environmental variations
• Capacitive coupling
Design clock distribution network carefully

12/4/2018 24
Timing closure

IC layout must satisfy geometric constraints, electrical

constraints, power & thermal constraints as well as
timing constraints
− Setup (long-path) constraints
− Hold (short-path) constraints
• Chip designers must complete timing closure −
Optimization process that meets timing constraints
− Integrates point optimizations discussed in previous
chapters, e.g., placement and routing, with specialized
methods to improve circuit performance

BITS Pilani, Pilani Campus

Components of timing closure

Components of timing closure covered;

• Timing-driven placement minimizes signal delays when
assigning locations to circuit elements
• Timing-driven routing minimizes signal delays when
selecting routing topologies and specific routes
• Physical synthesis improves timing by changing the netlist
− Sizing transistors or gates: increasing the width/ length
ratio of transistors to decrease the delay or increase the
drive strength of a gate
− Inserting buffers into nets to decrease propagation delays
− Restructuring the circuit along its critical paths
-- changing frequency of operation

BITS Pilani, Pilani Campus

 BITS Pilani
Pilani Campus

Memory element design

PERFORMANCE PARAMETERS
• clock load
• No. of transistors
• clocking scheme
• tsu, thold

12/4/2018 28
 Latch versus Register
 Latch • Register
stores data when
clock is low/ HIGH stores data when
clock rises
D Q D Q

Clk Clk

Clk Clk

D D

Q Q

12/4/2018 29
 Storage Mechanisms

Static Dynamic (soft node recharge-

based, charge leakage problem)
CLK
CLK

D Q
Q

CLK
CLK
D

CLK

12/4/2018 30
 Static-----Mux-Based Latch-1
Q = CLK’ . Q +CLK . D
CLK
CLK LOAD--4
Q
2 PHASE CLOCKING
CLK
10-TRANSISTORS
D

CLK

12/4/2018 31
 Mux-Based Latch(2)-
LESS CLK LOAD ,

CLK LOAD-2, 2 PHASE CLOCKING, 6-TRANSISTORS

CLK

D T1 I1

I2
CLK

12/4/2018 32
Mux-Based Latch(3)-
LESS CLK LOAD , Vt DEGRADATION

CLK
QM
CLK

QM

CLK

Non-overlapping clocks
CLK

NMOS only

12/4/2018 33
 Master-Slave (Edge-
Triggered) Register

Two opposite latches trigger on edge

Also called master-slave latch pair

12/4/2018 34
 Master-Slave Register

Multiplexer-based latch pair

I2 T2 I3 I5 T4 I6 Q

QM
D I1 T1 I4 T3

CLK

12/4/2018 35
TIMING METRICS
• T set up = I1+T1+I3+I2
• T CLK-Q = T3+ I6
• T HOLD = ~0
• Exact values can be obtained through
simulation

12/4/2018 36
 Reduced Clock Load
Master-Slave Register—
SIZING IMPORTANT-REVERSE CONDUCTION

CLK CLK

D T1 I1 T2 I3 Q

I2 I4
CLK CLK

I2 must be weak
when slave is on----reverse conduction

12/4/2018 37
 Timing Metrics
• T set up = T1+I1+I2
• T CLK-Q = T2+ I3
• T HOLD = ~0 (OR T1)
• exact values can be obtained through
simulation

12/4/2018 38
 Clock Overlap
CLK X CLK
Q
A
D
B

CLK CLK
(a) Schematic diagram

CLK

CLK
(b) Overlapping clock pairs

12/4/2018 39
Non overlapping phases

12/4/2018 40
Bistable Behavior

12/4/2018 41
SCHEMATIC

12/4/2018
 Overpowering the Feedback Loop
Cross-Coupled Pairs

NOR-based set-reset

S R Q Q
S
Q
S Q 0 0 Q Q
1 0 1 0
R Q
0 1 0 1
Q
R 1 1 0 0

Forbidden State

12/4/2018 43
12/4/2018
12/4/2018
Clocked

12/4/2018
12/4/2018
 Cross-Coupled NAND
-less transistors

Added clock
Cross-coupled NANDs VDD
Ratioed

S M2 M4
Q
Q
Q

Q CLK M6 M8 CLK
R M1 M3

S M5 M7 R

This is not used in datapaths any more,

but is a basic building memory cell

12/4/2018 48
Dynamic registers

12/4/2018 49
 TIMING METRICS
• T set up = T1
• T CLK-Q = I1+T2+ I2
• T HOLD = ~0 (or T1)
• EXACT VALUES CAN BE OBTAINED THROUGH SIMULATION

• IN OVERLAP--

12/4/2018 50
OVELAPS

12/4/2018 51
 Other Latches/Registers:
2
C MOS
VDD VDD

M2 M6

CLK M4 CLK M8
X
D Q
CL1 CL2
CLK M3 CLK M7

M1 M5

Master Stage Slave Stage

“Keepers” can be added to make circuit pseudo-static

12/4/2018 52
 Insensitive to Clock-Overlap
VDD VDD VDD VDD

M2 M6 M2 M6

0 M4 0 M8
X X
D Q D Q
1 M3 1 M7

M1 M5 M1 M5

(a) (0-0) overlap (b) (1-1) overlap

12/4/2018 53
Dual edge registers

12/4/2018 54
 Single phase clock
Latches/Registers: TSPC
VDD VDD VDD VDD

Out

In CLK CLK In CLK CLK

Out

Positive latch Negative latch

(transparent when CLK= 1) (transparent when CLK= 0)

12/4/2018 55
 Including Logic in TSPC
VDD VDD VDD VDD

In1 In2
PUN
Q Q

In CLK CLK CLK CLK

PDN In1

In2

Example: logic inside the latch

AND latch

12/4/2018 56
Reduced complexity

12/4/2018 57
 TSPC Register

VDD VDD VDD

CLK Q
M3 M6 M9
Y
Q
D CLK X CLK
M2 M5 M8

CLK
M1 M4 M7

12/4/2018 58
 Pulse-Triggered Latches
An Alternative Approach
Ways to design an edge-triggered sequential cell:

Master-Slave Pulse-Triggered
Latches Latch
L1 L2 L
Data Data
D Q D Q D Q

Clk Clk Clk Clk

Clk

12/4/2018 59
 Pulsed register-avoid race,
single latch
VDD VDD

M3 M6 VDD
CLK
Q
D CLKG CLKG MP CLKG
M2 M5
X

MN
M1 M4

(a) register (b) glitch generation

CLK

CLKG

(c) glitch clock

12/4/2018 60
 Pulsed Latches

CLK P1 P3
x Q

M6
M3

D P2 M5
M2

M4
M1 CLKD

12/4/2018 61
Sense amplifier based register

12/4/2018 62