Introduction to CMOS VLSI

Design
Engr. Annalyn D. Soria
 Why Make ICs
Integration improves
 size
 speed
 power
Integration reduce manufacturing costs
 (almost) no manual assembly
 Integrated circuits:
- defined as many transistors on one chip.
- it is in VLSI
 Scale of integration:
 SSI – Small Scale Integration (early 1970s)
contained 1 – 10 logic gates
 MSI – Medium Scale Integration
logic functions, counters
 LSI – Large Scale Integration
first microprocessors on the chip
 VLSI – Very Large Scale Integration
now offers 64-bit microprocessors, complete with cache
memory (L1 and often L2), floating-point arithmetic unit(s), etc.
 Complementary Metal Oxide Semiconductor
Fast, cheap, low power transistors
 VLSI Design Styles

 Full Custom
 Application-Specific Integrated Circuit (ASIC)
 Programmable Logic (PLD, FPGA)
 System-on-a-Chip
 Full Custom Design

 Each circuit element carefully “handcrafted”

 Huge design effort
 High Design & NRE (non recurring engineering Costs /
Low Unit Cost
 High Performance
 Typically used for high-volume applications
 Application-Specific Integrated
Circuit (ASIC)

 Constrained design using pre-designed (and

sometimes pre-manufactured) components
 Also called semi-custom design
 CAD tools greatly reduce design effort
 Low Design Cost / High NRE Cost / Med.
 Unit Cost
 Medium Performance
Programmable Logic (PLDs, FPGAs)

 Pre-manufactured components with programmable

interconnect
 CAD tools greatly reduce design effort
 Low Design Cost / Low NRE Cost / High Unit
 Cost
 Lower Performance
 System-on-a-chip (SOC)

Idea: combine several large blocks

 Predesigned custom cores (e.g., microcontroller) -
“intellectual property” (IP)
 ASIC logic for special-purpose hardware
 Programmable Logic (PLD, FPGA)
 Analog
Open issues
 Keeping design cost low
 Verifying correctness of design
 A Brief History
 1958: First integrated circuit
 Flip-flop using two transistors
 Built by Jack Kilby at Texas
Instruments
 2010 Courtesy Texas Instruments

 Intel Core i7 mprocessor

 2.3 billion transistors
 64 Gb Flash memory
 > 16 billion transistors

[Trinh09]
© 2009 IEEE.

9 1: Introduction
 Growth Rate
 53% compound annual growth rate over 50 years
 No other technology has grown so fast so long
 Driven by miniaturization of transistors
 Smaller is cheaper, faster, lower in power!
 Revolutionary effects on society

[Moore65]
Electronics Magazine

10 1: Introduction
 Invention of the Transistor
 Vacuum tubes ruled in first half of 20th century Large,
expensive, power-hungry, unreliable
 1947: first point contact transistor
 John Bardeen and Walter Brattain at Bell Labs

AT&T Archives.
Reprinted with
permission.

11 1: Introduction
 Transistor Types
 Bipolar transistors
 npn or pnp silicon structure
 Small current into very thin base layer controls large
currents between emitter and collector
 Base currents limit integration density
 Metal Oxide Semiconductor Field Effect Transistors
 nMOS and pMOS MOSFETS
 Voltage applied to insulated gate controls current
between source and drain
 Low power allows very high integration

12 1: Introduction
 MOS Integrated Circuits
 1970’s processes usually had only nMOS transistors
 Inexpensive, but consume power while idle

Intel
Museum.
[Vadasz69]
Reprinted
© 1969 IEEE. with
permission.

Intel 1101 256-bit SRAM Intel 4004 4-bit mProc

 1980s-present: CMOS processes for low idle power

13 1: Introduction
 And Now…

14 1: Introduction
 Feature Size

 Minimum feature size shrinking 30% every 2-3 years

15 1: Introduction
 Silicon Lattice
 Transistors are built on a silicon substrate
 Silicon is a Group IV material
 Forms crystal lattice with bonds to four neighbors

Si Si Si

Si Si Si

Si Si Si

16 1: Introduction
 Dopants
 Silicon is a semiconductor
 Pure silicon has no free carriers and conducts poorly
 Adding dopants increases the conductivity
 Group V: extra electron (n-type)
 Group III: missing electron, called hole (p-type)

Si Si Si Si Si Si
- +

+ -
Si As Si Si B Si

Si Si Si Si Si Si

17 1: Introduction
 nMOS Operation Cont.
 When the gate is at a high voltage:
 Positive charge on gate of MOS capacitor
 Negative charge attracted to body
 Inverts a channel under gate to n-type
 Now current can flow through n-type silicon from
source through channel to drain, transistor is ON

Source Gate Drain

Polysilicon
SiO2

1
n+ n+
S D
p bulk Si

18 1: Introduction
 pMOS Transistor
 Similar, but doping and voltages reversed
 Body tied to high voltage (VDD)
 Gate low: transistor ON
 Gate high: transistor OFF
 Bubble indicates inverted behavior

Source Gate Drain

Polysilicon
SiO2

p+ p+

n bulk Si

19 1: Introduction
 Power Supply Voltage

 GND = 0 V
 In 1980’s, VDD = 5V
 VDD has decreased in modern processes
 High VDD would damage modern tiny transistors
 Lower VDD saves power
 VDD = 3.3, 2.5, 1.8, 1.5, 1.2, 1.0, …

20 1: Introduction
 Complementary CMOS
 Complementary CMOS logic gates
 nMOS pull-down network
 pMOS pull-up network pMOS
pull-up
 a.k.a. static CMOS network
inputs
output

nMOS
pull-down
network
Pull-up OFF Pull-up ON
Pull-down OFF Z (float) 1

Pull-down ON 0 X (crowbar)

21 1: Introduction
 Transistors as Switches
 We can view MOS transistors as electrically controlled
switches
 Voltage at gate controls path from source to drain

g=0 g=1

d d d
nMOS g OFF
ON
s s s

d d d

pMOS g OFF
ON
s s s

22 1: Introduction
 Series and Parallel
a a a a a
0 0 1 1
g1
g2
0 1 0 1
b b b b b
(a) OFF OFF OFF ON


a a a a
nMOS: 1 = ON g1
a
0 0 1 1


g2
pMOS: 0 = ON b
0
b
1
b
0
b
1
b


(b) ON OFF OFF OFF

Series: both must be ON

a


a a a a

Parallel: either can be ON g1 g2 0 0 0 1 1 0 1 1

b b b b b

(c) OFF ON ON ON

a a a a a

g1 g2 0 0 0 1 1 0 1 1
b b b b b

(d) ON ON ON OFF

23 1: Introduction
 Conduction Complement

 Complementary CMOS gates always produce 0 or 1

 Rule of Conduction Complements

 Pull-up network is complement of pull-down
 Parallel -> series, series -> parallel

24 1: Introduction
 CMOS Inverter
A Y VDD
0 1
1 0 OFF
ON
0
1
A Y
ON
OFF

A Y
GND
25 1: Introduction
 CMOS NAND Gate
A B Y
ON
OFF
OFF
ON OFF
ON
0 0 1
0 1 1
1
0
Y
1 0 1 ON
A OFF

1 1 0 0
1
1
0
OFF
ON
B ON
OFF

26 1: Introduction
 CMOS NOR Gate
A B Y
0 0 1 A
0 1 0
1 0 0 B
1 1 0 Y

27 1: Introduction
 Compound Gates
 Compound gates can do any inverting function
 Ex: AND-AND-OR-INV (A2OI2) Y  ( A  B)  (C  D)

A C A C
B D B D
(a) (b)

C D
A B C D
A B
(c)
(d)

C D
A
A B
B
Y Y
C
A C
D
B D
(f)

(e)
 Example: O3AI

Y  ( A  B  C)  D
 Example: O3AI

Y  ( A  B  C)  D

A
B
C D
Y
D
A B C