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Basic Scan

The document discusses design for testability (DFT) and basic scan design concepts. It introduces DFT and why it is needed to address increasing test complexity. It then describes testability, different scan cell designs, scan architectures like full scan and partial scan, and the basic scan design flow. The goal of DFT and scan design is to improve the controllability and observability of a circuit to simplify testing.

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saikumar bhavana
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1K views20 pages

Basic Scan

The document discusses design for testability (DFT) and basic scan design concepts. It introduces DFT and why it is needed to address increasing test complexity. It then describes testability, different scan cell designs, scan architectures like full scan and partial scan, and the basic scan design flow. The goal of DFT and scan design is to improve the controllability and observability of a circuit to simplify testing.

Uploaded by

saikumar bhavana
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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DFT and Basic SCAN

• Introduction

• What is DFT? Why it is required?

• Importance of Testing.

• What is Testability?

• Design for Testability Basics

• Scan Cells Designs

• Scan Architectures

• Scan Design Rules

• Scan Design Flow


Introduction

 History

 Various testability measures & ad-hoc testability enhancement methods

- To improve testability of a design.


- To ease sequential ATPG.
- Still quite difficult to reach more than 90% fault coverage.

 Structured DFT

- To conquer the difficulties in controlling and observing the internal states of sequential circuits.
- Scan design is the most popular structured DFT approach.
What is DFT?

• DFT refers to the hardware design styles, or added hardware that reduces test generation complexity.

• Motivation :- Test generation complexity increases exponentially with the size of design.

• Basically DFT enables the manufacturing test.

• It is a structural technique, which facilitates a design to become testable after production.


WHY DFT
• To increase Productivity:

Shorter time -to-market :- DFT ensures the release of the chip into the market within the

specified time without any defects.

Reduced cost:- Testing and debugging the chip with low cost.

Reduces the test complexity, test time and tester requirements.

• To Improve Quality:

Detect the manufacturing defects early in the design stage.

Reduced Defects per million(DPM)

Improved quality of test : - Means improving test coverage to the required percentage.
Importance of Testing
• Since times design size is decreasing.

• Defects are unavoidable.

• Testing is required to guarantee fault- free chips.

• Product quality depends on following parameters

Test cost

Test quality

Test time

• Hence DFT came into existence to deliver the cost effective, defect-free quality designs.
What is Testability?

• The ability to put the design into a known initial state, and then control and observe internal signal
values.

• Two basic properties determines the testability of a node are :-

Controllability : The ability to set node to a specific value.

Observability : The ability to observe a node’s value.


Ad Hoc Approach

Typical ad hoc DFT techniques


• Insert test points

• Avoid asynchronous set/reset for storage elements

• Avoid combinational feedback loops

• Avoid redundant logic

• Avoid asynchronous logic

• Partition a large circuit into small blocks


Ad-hoc Approach - Test Point Insertion

OP2 shows the


structure of an
observation,
which is
composed of a
multiplexer
(MUX) and a D
flip-flop.

Observation Point Insertion


Ad-hoc Approach - Test Point Insertion

A MUX is inserted between the


source and destination ends.

During normal operation:


TM = 0 ,such that the value
from the source end drives the
destination end through the 0
port of the MUX.

During test TM = 1,such that the


value from the D flip-flop drives
the destination end through the
1 port of the MUX.
Control point insertion
Structured Approach

Scan design

• Convert the sequential design into a scan design


• Three modes of operation
- Normal mode
-All test signals are turned off
-The scan design operates in the original functional configuration
- Shift mode
- Capture mode
-In both shift and capture modes, a test mode signal TM is
often used to turn on all test-related fixes
Scan Insertion
• Scan Insertion goal is to increase the controllability and observability of a circuit.

• The most common is scan design technique which modifies the internal sequential circuit.

• Scan circuit facilitates test generation and can reduce external tester usage.

• Internal scan is the modification of design’s circuitry to increase its testability with
two states mainly - shift & capture depending on SCAN_ENABLE.

• Achieving this goal involves replacing sequential elements with scan cells and stitching them together into
scan registers or scan chains.
Scan Cell Design

 A scan cell has two inputs: data input and scan input
• In normal/capture mode, data input is selected to update the output

• In shift mode, scan input is selected to update the output

 Three widely used scan cell designs


- Muxed-D Scan Cell

- Clocked-Scan Cell

- LSSD Scan Cell


Muxed-D Scan cell

• This scan cell is composed of a D


flip-flop and a multiplexer.

• The multiplexer uses an additional


scan enable input .SE to select
between the data input Dl and the
scan input Sl.

Clocked Scan cell

• In the clocked-scan cell,


input selection is conducted
using two independent clocks,
DCK and SCK.
LSSD Scan Cell
An LSSD scan cell is
used for level-sensitive
latch base designs.

This scan cell contains


two latches, a master 2-
port D latch L1 and a slave
D latch L. Clocks C,
A and B are used to select
between the data input D
and the scan input I to
drive +LI and +L2. In an
LSSD design, either +LI
or +L2 can be used to
drive the combinational
logic of the design.
SCAN ARCHITECTURES

 Full-Scan Design
• All or almost all storage element are converted into scan cells.

 Partial-Scan Design
• A subset of storage elements are converted into scan cells.

 Partition Scan Design


FULL SCAN DESIGN

To form a scan chain,


the scan input SI of
SFF2 and SFF3 are
connected to the output
Q of the previous scan
cell, SFF1 and SFF2
respectively.
In addition, the scan input
SI of the first scan cell
SFF1 is connected to
the primary Input SX
and the output Q of the
last scan cell SFF3 is
connected to the
primary output SO.
Partial-Scan Design

A scan chain is constructed


With two scan cells SFF1 and
SSF3, while flip-flop FF2 is
Left out.
It is possible to reduce the test
generation complexity by
splitting the single clock into
two separate clocks, one for
controlling all non-scan storage
elements.
However, this may result in
Additional complexity of routing
An example of muxed -D two separate clock trees during
partial scan design physical implementation.
Random-Access Scan Design

 Advantages of RAS:

• Can control or observe individual scan cells without affecting others


• Reduce test power dissipation
• Simplify the process of performing delay test

 Disadvantages of traditional RAS:

• High overhead in scan design and routing


• No guarantee to reduce the test application time
Random Access Design

All scan cells are


organized into a
two-dimensional
array. A [log2^n]
bit address shift
register, where n is
the total number of
scan cells, is used to
specify which scan
cell to access.
SCAN DESIGN FLOW

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