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RISC vs. CISC

This document compares RISC and CISC processor architectures. CISC processors use complex instruction sets with instructions that manipulate low-level elements like memory in one clock cycle, leading to smaller code sizes but higher cycles per instruction. RISC processors use simpler instruction sets that operate in one clock cycle, leading to larger code sizes but lower cycles per instruction. Examples of CISC processors include System/360 and Intel x86, while RISC examples include ARM processors in iPods, iPhones, and game consoles.

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131 views12 pages

RISC vs. CISC

This document compares RISC and CISC processor architectures. CISC processors use complex instruction sets with instructions that manipulate low-level elements like memory in one clock cycle, leading to smaller code sizes but higher cycles per instruction. RISC processors use simpler instruction sets that operate in one clock cycle, leading to larger code sizes but lower cycles per instruction. Examples of CISC processors include System/360 and Intel x86, while RISC examples include ARM processors in iPods, iPhones, and game consoles.

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afaaki
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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RISC vs.

CISC

By Chiam D Cook
Cs 147 spring 08
CISC
• Complex Instruction Set Computer
– Large number of complex instructions
– Low level
– Facilitate the extensive manipulation of low-
level computational elements and events such
as memory, binary arithmetic, and
addressing.
CISC Examples
• Examples of CISC processors are the
– System/360(excluding the 'scientific' Model
44),
– VAX,
– PDP-11,
– Motorola 68000 family
– Intel x86 architecture based processors.
Pro’s
• Emphasis on hardware
• Includes multi-clock complex
instructions
• Memory-to-memory:
"LOAD" and "STORE"
incorporated in instructions
• Small code sizes,
high cycles per second
• Transistors used for storing
complex instructions
Con’s
• That is, the incorporation of older instruction sets
into new generations of processors tended to force
growing complexity.
• Many specialized CISC instructions were not
used frequently enough to justify their existence.
• Because each CISC command must be translated
by the processor into tens or even hundreds of
lines of microcode, it tends to run slower than an
equivalent series of simpler commands that do
not require so much translation.
The CISC Approach
• MULT 2:3, 5:2
RISC
• Reduced Instruction Set Computer
– Small number of instructions
– instruction size constant
– bans the indirect addressing mode
– retains only those instructions that can be
overlapped and made to execute in one machine
cycle or less.
RISC Examples
• Apple iPods (custom ARM7TDMI SoC)
• Apple iPhone (Samsung ARM1176JZF)
• Palm and PocketPC PDAs and smartphones (Intel
XScale family, Samsung SC32442 - ARM9)
• Nintendo Game Boy Advance (ARM7)
• Nintendo DS (ARM7, ARM9)
• Sony Network Walkman (Sony in-house ARM
based chip)
• Some Nokia and Sony Ericsson mobile phones
Pro’s
• Emphasis on software
• Single-clock,
reduced instruction only
• Register to register:
"LOAD" and "STORE"
are independent instructions
• Low cycles per second,
large code sizes
• Spends more transistors
on memory registers
The RISC Approach
• LOAD A, 2:3
LOAD B, 5:2
PROD A, B
STORE 2:3, A
Performance
Performance
• The CISC approach attempts to
minimize the number of
instructions per program,
sacrificing the number of cycles
per instruction. RISC does the
opposite, reducing the cycles per
instruction at the cost of the
number of instructions per
program.

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