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RS Flip Flop

The document discusses RS flip flops which contain two NOR or NAND gates cross-coupled, where the output of one gate is fed back as input to the other gate, and can be set or reset based on the signals applied to the R and S inputs to change the states of the Q and Q' outputs. RS flip flops have a truth table that defines the output states based on the input combinations and some combinations like R and S both high are forbidden as they violate the requirement that Q and Q' must be complements. Clocked D flip flops have one D input and an enable input, where the output follows the D input when enabled and

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962 views14 pages

RS Flip Flop

The document discusses RS flip flops which contain two NOR or NAND gates cross-coupled, where the output of one gate is fed back as input to the other gate, and can be set or reset based on the signals applied to the R and S inputs to change the states of the Q and Q' outputs. RS flip flops have a truth table that defines the output states based on the input combinations and some combinations like R and S both high are forbidden as they violate the requirement that Q and Q' must be complements. Clocked D flip flops have one D input and an enable input, where the output follows the D input when enabled and

Uploaded by

Nelson Raja
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PPT, PDF, TXT or read online on Scribd
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RS Flip Flops

Flip Flops

 A flip flop is an electronic circuit with two stable


states that can be used to store binary data in one
binary digit (bit).
RS Flip Flops
 RS flip flop contains two NOR gates and the two NOR
gates are cross-coupled.

 The output of NOR A is fed back to one of the inputs of


NOR B and S is the another input to NOR B.

 The output of NOR B is fed back to one of the inputs of


NOR A and R is the another input to NOR A.

 Q is the output of NOR A gate.

 Q’ is the output of NOR B gate.


RS Flip Flops

Output

B
RS flip-flop Truth Table RS flip-flop Symbol
RS Flip Flops
 The RS stands for SET/RESET. It has two inputs, one is called “SET”
which will set the device (output = 1) and is labeled S and another input
is known as “RESET” which will reset the device (output = 0) labeled as
R.

 The output of flip-flop t requires Q to be the complement of Q’.

 I. The first input condition in the truth table is R = 0 and S = 0 has no


effect on its output, so the flip-flop simply remains in its present state;
that is, Q remains unchanged.

 2. The second input condition R = 0 and S = 1 forces the output of NOR


gate B low. Both inputs to NOR gate A are now low, and the A NOR-
gate output must be high. So the, 1 at the S input is said to SET the flip-
flop, and it switches to the stable state where Q = 1.
RS Flip Flops
 3. The third input condition is R = 1 and S = 0. This condition forces the
output of NOR gate A low, and since both inputs to NOR gate B are
now low, the output must be high. Thus a 1 at the R input is said to
RESET the flip-flop-'-and it switches to the stable state where Q = 0 (or
Q = 1).

 4. The last input condition in the table, R = 1 and S = 1, is forbidden, as


it forces the outputs of both NOR gates to the low state. In other words,
both Q = 0 and Q’ = 0 at the same time. But this violates the basic
definition of a flip-flop that requires Q to be the complement of Q’. So
this condition is forbidden.
(NAND Gate RS Flip Flop)

 NAND Gate Flip Flop or RS flip flop contains two NAND


gates and the two NAND gates are cross-coupled.

 The output Q of NAND A is fed back to one of the inputs of


NAND B and is the another input to NAND B.

 The output of NOR B is fed back to one of the inputs of


NAND A and is the another input to NAND A.

 Q is the output of NAND A gate.

 Q’ is the output of NAND B gate.


A

Output

B
NANO-Gate
RS Flip-Flops
When R=S=0 is combination is called a restricted
combination. As both NAND gates then output = 1,

it breaks the logical equation Q = not Q.

R S Q Q’
0 0 Restricted

0 1 0 1
1 0 1 0
1 1 X X
RS Flip-Flops
Summary: RS Flips flops can be made with NOR gates or
NAND gates. NOR gates use Positive Logic Levels. NAND
gates use Negative Logic Levels

R S Q Q’ Q Q’

0 0 Last State 0 0
Forbidden
0 1 1 0 0 1 0 1
1 0 0 1 1 0 1 0

1 1 Forbidden 1 1 Last State


Clocked D Flip-Flops
 A D (Data) flip-flop has one
input.
 This flip-flop is disabled
when EN is low, but is
transparent when EN is
high.
 If EN is high then D and
Output values are same.
 If EN is low then the output
remains unchanged (ie last
state).
 This kind of D flip-flop is
often called a D latch.

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