Design for Testability Theory and Practice

Lecture 6: Combinational
ATPG
 ATPG problem
 Example
 Algorithms
Multi-valued algebra
D-algorithm
Podem
Other algorithms
 ATPG system
 Summary

Copyright 2001, Agrawal & Bushnell Day-1 PM Lecture 6 1

 ATPG Problem
 ATPG: Automatic test pattern generation
Given
 A circuit (usually at gate-level)
 A fault model (usually stuck-at type)
Find
 A set of input vectors to detect all modeled faults.
 Core solution: Find a test vector for a given fault.
 Combine the “core solution” with a fault
simulator into an ATPG system.

Copyright 2001, Agrawal & Bushnell Day-1 PM Lecture 6 2

 What is a Test?
Fault activation
Fault effect
X Combinational circuit
1
0
0 1/0 1/0
Primary inputs
1 Primary outputs
(PI)
0 (PO)
1
X
X

Path sensitization
Stuck-at-0 fault

Copyright 2001, Agrawal & Bushnell Day-1 PM Lecture 6 3

 Multiple-Valued Algebras
Symbol Alternative Fault-free Faulty
Representation circuit Circuit

D 1/0 1 0
D 0/1 0 1
Roth’s
0 0/0 0 0
Algebra
1 1/1 1 1
X X/X X X
G0 0/X 0 X
Muth’s
G1 1/X 1 X
Additions
F0 X/0 X 0
F1 X/1 X 1

Copyright 2001, Agrawal & Bushnell Day-1 PM Lecture 6 4

 An ATPG Example
1 Fault activation
2 Path sensitization
3 Line justification

1
D

Copyright 2001, Agrawal & Bushnell Day-1 PM Lecture 6 5

 ATPG Example (Cont.)
1 Fault activation
2 Path sensitization
3 Line justification
1
D
D
1 D
D
0
1

Copyright 2001, Agrawal & Bushnell Day-1 PM Lecture 6 6

 ATPG Example (Cont.)
1 Fault activation
2 Path sensitization
3 Line justification
1
D
D
1 D Conflict
0 D
1
1
1
1

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 ATPG Example (Cont.)
1 Fault activation
Backtrack 2 Path sensitization
3 Line justification

0 D
1 D
D

1 D 1
D

Copyright 2001, Agrawal & Bushnell Day-1 PM Lecture 6 8

 ATPG Example (Cont.)
1 Fault activation
2 Path sensitization
3 Line justification

0 D
1 D
D

1 D 1
D
1

Test found
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 D-Algorithm (Roth 1967)
 Use D-algebra
 Activate fault
 Place a D or D at fault site
 Justify all signals
 Repeatedly propagate D-chain toward POs through a gate
 Justify all signals
 Backtrack if
 A conflict occurs, or
 All D-chains die
 Stop when
 D or D at a PO, i.e., test found, or
 Search exhausted, no test possible

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 Example: Fault A sa0
 Step 1 – Fault activation – Set A = 1

D
1 D

D-frontier = {e, h}

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 Example Continued
 Step 2 – D-Drive – Set f = 0

0
D
1 D D

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 Example Continued
 Step 3 – D-Drive – Set k = 1

1
D
0
D
1 D
D

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 Example Continued

 Step 4 – Consistency – Set g = 1

1
1 D
0
D
1 D D

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 Example Continued
 Step 5 – Consistency – f = 0 Already set

1
1
D
0
D
1 D D

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 Example Continued
 Step 6 – Consistency – Set c = 0, Set e = 0

1
0 1
D
0
0
D
1 D D

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 Example: Test Found
 Step 7 – Consistency – Set B = 0
 Test: A = 1, B = 0, C = 0, D = X

X
1
0 1 D
0 0
0
D
1 D D

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 Podem (Goel, 1981)
 Podem: Path oriented decision making
 Step 1: Define an objective (fault activation, D-drive, or line
justification)
 Step 2: Backtrace from site of objective to PIs (use
testability measures guidance) to determine a value for a PI
 Step 3: Simulate logic with new PI value
 If objective not accomplished but is possible, then
continue backtrace to another PI (step 2)
 If objective accomplished and test not found, then
define new objective (step 1)
 If objective becomes impossible, try alternative
backtrace (step 2)
 Use X-PATH-CHECK to test whether D-frontier still there –
a path of X’s from a D-frontier to a PO must exist.

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 Podem Example
3. Logic simulation for A=0 2. Backtrace “A=0” 1. Objective “0”

S-a-1

(9, 2)

4. Objective possible but not accomplished

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 Podem Example (Cont.)
6. Logic simulation for A=0, B=0
5. Backtrace “B=0” 1. Objective “0”

0
0
0
S-a-1

0
(9, 2)

7. Objective possible but not accomplished

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 Podem Example (Cont.)
9. Logic simulation for E=0
8. Backtrace “E=0” 1. Objective “0”

0
0
0
0
0
S-a-1

0
(9, 2)

10. Objective possible but not accomplished

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 Podem Example (Cont.)
12. Logic simulation for D=0
1. Objective “0”

0
0
0
0
0
S-a-1

0 0
(9, 2)
0

13. Objective accomplished 11. Backtrace “D=0”

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 An ATPG System
Random pattern
generator

Fault simulator
yes

Fault Random Deterministic

Save coverage patterns ATPG (D-alg.
patterns yes improved? no effective? no or Podem)

Stop if fault coverage goal achieved

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 Summary
 Most combinational ATPG algorithms use D-algebra.
 D-Algorithm is a complete algorithm:
 Finds a test, or
 Determines the fault to be redundant
 Complexity is exponential in circuit size
 Podem is also a complete algorithm:
 Works on primary inputs – search space is smaller than that of
D-algorithm
 Exponential complexity, but several orders faster than D-
algorithm
 More efficient algorithms available – FAN, Socrates, etc.
 See, M. L. Bushnell and V. D. Agrawal, Essentials of Electronic
Testing for Digital, Memory and Mixed-Signal VLSI Circuits,
Springer, 2000, Chapter 7.

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 Exercise 2: Lectures 4-6

 For the circuit shown above

 Determine SCOAP testability measures.
 Derive a test for the stuck-at-1 fault at the output of
the AND gate.
 Using the parallel fault simulation algorithm,
determine which of the four primary input faults are
detectable by the test derived above.

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 Exercise 2: Answers
■ SCOAP testability measures, (CC0, CC1) CO, are shown below:

(1,1) 4
(2,3) 2
(1,1) 4 (4,2) 0

(1,1) 3
(1,1) 3

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 Exercise 2: Answers Cont.

■ A test for the stuck-at-1 fault shown in the diagram is 00.

0 0 D
D
0 s-a-1

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 Exercise 2: Answers Cont.

■ Parallel fault simulation of four PI faults is illustrated below.

Fault PI2 s-a-1 is detected by the 00 test input.

00100 00000
PI1=0
00001
00001
PI2=0

PI2 s-a-1 detected

00001
00001
No fault

PI2 s-a-1
PI1 s-a-0
PI1 s-a-1
PI2 s-a-0

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