UNIT VI -

VLSI TESTING &

ANALYSIS
Workshop outline
• Types of Faults
• Need of Design for Testability
• Fault Models
• Path Sensitizing
• Sequential Circuit Test
• BIST
• Test Pattern Generation
• JTAG & Boundary Scan
• TAP Controller

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Types of Faults
Errors : An instance of an incorrect operation of the system being tested is referred
to as observed error
Design Errors Fabrication Fabrication Defects Physical Failure
 Incomplete  Wrong  Imperfect  Environmental
specification components manufacturing factors
Violation of  incorrect wiring process  Component
design rules  Short caused by  Improper doping wear out
 Incorrect mapping incorrect soldering profiles
between different  Mask alignment
level of designs errors
 Poor encapsulation

Fabrication Fabrication Physical Physical

Errors + Defects + Failures = Faults

 Physical fault do not allow direct mathematical treatment of testing and

diagnosis solution is to deal with logical faults.
 Basic Assumption regarding the nature of logical faults are referred as fault
mode NESGI FOE 3
Types of faults Cont …
Faults Defects in silicon substrate,
caused by Photolithographic defects
physical Oxide effects
defects Process variations and abnormalities

Physical Shorts (Bridging faults)

defects can Opens
cause Resistive shorts and opens
electrical Excessive change in threshold voltage
faults

Electrical
Logical stuck-at-0 or suck-at-1
faults
Slower transition (Delay fault)
translate
And bridging , OR bridging
into logical
faults

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Need of Design for Testability
• 3 important attribute to testability are
– Controllability :
• Ability to establish a specific signal value at each node in a circuit by setting
values on the circuit’s input
– Obsevability :
• Ability to determine the signal value at any node in a circuit by controlling
the circuit’s inputs and observing the output
– Predictability :
• Ability to obtain known output values in response to given input input stimuli.

NOR
C1
Gate
.. C2

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• Two types of test inputs
CP – Control point OP – Observation point
enhance controllability enhance obsevability
Jumper
G
C1
NOR
Gate A A .. C2
’
OP CP
G*
NOR
C1 Op= make the signal G*
Gate
CP
.. C2
directly observable

G* G’
C1
NOR
Gate
OR Gate .. C2

CP1
CP2
CP1=CP2=0, G’=G= normal opreation
CP1=1 G*=0 G’= CP2
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Testability
 Test Generation :
 Process of determining the stimuli necessary to test digital simulation

 Testability is a design characteristics that influence various cost associated with test

 Design for testability technique are design efforts specially employed to ensure that
a device is testable

 Test complexity can be converted into cost associated with the testing process.
Several fact to this cost are :
 Cost of pattern generation
 Cost of fault simulation
 Generation of fault location information
 Cost of equipements
 Cost related to testing process itself

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Testability Cont…

exceed
Cost of Cost of
test Cost of maintaini
Design
Generati manufact ng
Cost
on uring system

Goal is to keep them in Process called design for

reasonable bounts testability

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Fault Models
• Stuck at Model

• Bridging Fault Model

• Multiple Stuck Model

• Delay Fault Model

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Stuck at Model

• Wires permanently being stuck at logic value 0 or 1.

• Stuck –at-0 denoted as w/0.
• stuck-at-1 denoted as w/1.

a
W1 OR
GATE f

b
W2 AND
d
GATE
W3 c

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False Detected by Various Input Valuations

Test Z a/0 a/1 b/1 c/0 c/1 d/0 d/1 f/0 f/1
000 0 0
001 0 0
010 0 0
011 1 1
100 1 0
101 1 0
110 1 0
111 1 1

Test Set : A Complete set of test used for a given circuit is referred to as a test
set. {100,101 and 110}

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False Detected by Various Input Valuations

Test a/0 a/1 b/0 b/1 c/0 c/1 d/0 d/1 f/0 f/1
000
001
010
011
100
101
110
111

Test Set : A Complete set of test used for a given circuit is referred to as a test
set.
Test Set = {001,010,011,100}
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Definitions
• Test Vector : An input vector for the circuit under test that causes the
presence of a fault to be observable at a primary output

• Detected faults : A fault for which a valid test vector has been generated.

• Undetected Faults : A fault for which a test vector has not been generated.

• Fault Coverage : the percentage of total fault for which test pattern have
been generated.

• Fault Efficiency : The percentage of faults that either are detected or proven
redundant.

• Redundant Fault : A fault for which no test pattern exist.

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 x1

x2
Combo Circuit
x3 z

x4

z  ( x 2  x3) x1  x 1 x 4
Q. Let fault be x4 stuck-at-0. Generate the test set for detection of fault?

T={ }

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Bridging Fault Model

• A test vector t detects a fault f if and only if z f (t )  z (t )

0
x1 AND
z1
OR GATE
x2
1
AND
z2
x3 GATE
1

• Does Test detects the OR bridging fault : Yes or No?

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Multiple Bridging Fault
N
a NAND
GATE
NAND
b GATE
Z
NAND M

c GATE

a b c Z c s-a-0 c s-a-0 &

a s-a 1
0 0 0 0 0 0
0 0 1 0 0 0
0 1 0 0 0 1
0 1 1 1 0 1
1 0 0 0 0 0
1 0 1 0 0 0
1 1 0 1 1 1
1 1 1 1 1 1
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Multiple Bridging Fault
N
a NAND
GATE
NAND
b GATE
Z
NAND M

c GATE

a b c Z c s-a-0 c s-a-0 &

a s-a 1
0 0 0 0 0 0
0 0 1 0 0 0
0 1 0 0 0 1
0 1 1 1 0 1
1 0 0 0 0 0
1 0 1 0 0 0
1 1 0 1 1 1
1 1 1 1 1 1
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Path Sensitizing
• A better alternative is to deal with several wires that form a path an entity
that can be tested for several faults using a single test

a
W1 AND b
W2=1 GATE
c
NOR f
GATE AND
W3 = 0 GATE
W4 =1

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Derive a Test Set based on Sensitized Path

W1 c
AND
GATE
W2
NOT OR
GATE GATE
f
b AND
GATE W4
d
W3

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Steps

• Define probable paths from inputs to output

– Path 1 : W1-c-f
– Path 2 : W2-c-f
– Path 3 : W2-b-d-f
– Path 4 : W3-d-f
– Path 5 : W4-f
• Apply path sensitization technique
– W2 = 1, W3 = x, W4 = 0 therefore the test become as
– W1W2W3W4 = 01x0 = 0100,0110
– = 11x0 = 1101,1110
• Find the final test set

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 Sequential Circuit Test
• A combinational circuit is tested by comparing its behavior with
functionality specified in truth table.
• Similarly a sequential circuit is tested by comparing its behavior with the
functionality specified in the state table.
• A general model for sequential circuit
Z1 – Zm
Primary o/p’s
W1 – Wn
Combinational Circuit
Primary i/p’s

Present Next
Y1 Y1 state
state
variable - - variable
yk YK

Que. How to apply test vectors on present state input how to observe values on next
state output? NESGI FOE 21
Scan Path Arrangement
Scan out

Q2 D2 A Y2

Mux1

clk normal / scan

A
Q1 D1
Y1
y1 Mux2

Scan in
B
0101 1001

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 Q1

W
AND
Q2
W
AND OR Y1
W
Q1 AND OR
Q1 Y2 START
Q2
Y1
AND
Z
Scan out Scan in test vector into flip-
Q2 D2 A Y2 flop by setting scan =1
y2
Mux1
Apply W1-WN test vector
and perform manual
B
operations

clk normal / scan Observe Z1-Zm

Load generated output Y1-

A YK into flip-flop
Q1 D1
Y1
y1 Mux2
Select input keeping scan
B =1 and contents are
scanned out
Scan in - 01
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Built In Self Test
• The technique to incorporate the testing capability within the circuit itself.
• Generate a test vectors, apply them to the circuit under test and then check
the response.
Test pattern Circuit Test Result Signature
Generation Under Test Compressor

• A small probability that signature of a faulty circuit with the same as good
circuits is called as aliasing or error masking given by
2 Lr  1
P
2L 1
• where
L – length of test sequence
r – length of signature register
P – probability of aliasing

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 + Q0 Q1 Q2
1 0 0
D0 Q0 D1 Q1 D2 Q2 0 1 0

1 0 0

Q2
NAND
GATE
Q1

NAND Zf= 0101110 0

GATE
Z = 0100110 0
NAND
NOT GATE Z Q0 Q1 Q2 Zf Q0 Q1 Q2
Q0 GATE 0 0 0 0 0 0 0 0
1 0 0 0
0 1 0 0
+
0 0 1 0

+ D0 R0 D1 R1 D2 R2
1 1 0 1

Z 1 0 1 0
0 0 0 0 0 0 1
25
0 1 0 0

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 + Q0 Q1 Q2
1 0 0
D0 Q0 D1 Q1 D2 Q2 0 1 0
1 0 1
1 0 0
1 1 0
1 1 1
0 1 1
Q2
NAND 0 0 1
GATE 1 0 0
Q1

NAND Zf= 0101110 0

GATE
Z = 0100110 0
NAND
NOT GATE Z Q0 Q1 Q2 Zf Q0 Q1 Q2
Q0 GATE 0 0 0 0 0 0 0 0
1 0 0 0 1 0 0 0
0 1 0 0 0 1 0 0
+
0 0 1 0 1 0 1 0

+ D0 R0 D1 R1 D2 R2
1 1 0 1 1 0 0 1

Z 1 0 1 0 1 0 0 0
0 0 0 0 0 0 1 0 1 0 0
26
0 1 0 0 0 0 1 0

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Test Pattern Generation
• Test patterns are generated either by using :
– Pseudo random pattern generator
f ( x)  x 3  x  1

f ( x)  x m  am 1 x m 1  a1 x  1
 x 3  a2 x 2  a1 x  1
– Weighted test generator

– Adaptive Test Generator

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 Q0 Q1 Q2
1 1 1
Case I
f ( x)  x 3  x  1

D0 Q0 D1 Q1 D2 Q2

1 1 1

Case II Q0 Q1 Q2
1 1 1
f ( x)  x 3  x 2  1

D0 Q0 D1 Q1 D2 Q2
1110100
1 1 1

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 Q0 Q1 Q2
1 1 1
Case I
0 1 1
f ( x)  x 3  x  1 0 0 1
1 0 0
+
0 1 0
1 0 1
D0 Q0 D1 Q1 D2 Q2
1 1 0

1 1 1 1110010 1 1 1

Case II Q0 Q1 Q2
1 1 1
f ( x)  x 3  x 2  1
0 1 1
+ 1 0 1
0 1 0

D0 Q0 D1 Q1 D2 Q2 0 0 1

1110100 1 0 0
1 1 1 1 1 0
1 1 1

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JTAG Boundary Scan
• To Ensure test development and testing of boards containing
these VLSI chip.
• Significantly more effective & less costly
– Joint Action Test Group (JTAG) Boundary Scan Standerd
– IEEE 1149.1 testability bus standard.
• To allow for efficient testing of board interconnect and to
facilitate isolation and testing of chips either via the test bus
or built in self test hardware.

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 IC with boundary scan register and
Test Access Port
Test bus circuitry consist of :
• A Test Access Port
consisting of the ports Boundary scan
associated with TMS, TCK, cells
TDI & TDO
• A TAP controller
• A scanable instruction
register & associated logic. Core Logic
• A group of scanable test
data register

Test Logic & TAP

Controller

Test data input Test Where

Control of test bus Test CLK Test
Test
data • Test clock (TCK)
reset
circuitry is carried out by mode
output • A test mode signal (TMS)
TAP controller in select • Test data input (TDI)
response to state NESGI FOE
• Test data output (TDO)
31
transitions on TMS line.
 Operation of test bus in associated logic :
1.Instruction is sent serially over TDI line into the instruction register.
2.Selected test circuitry is configured to respond to the instruction.
3.Test instruction is executed

Boundary Scan Cell : SOUT

IN
MUX OUT

MUX D Q D Q

A B
Mode_Control

SIN
ClockDR UpdateDR
ShiftDR

Cell operate in four modes:

Normal mode : Port IN to Port Out Scan Mode : Connection from SIN to SOUT
Capture Mode : From Port IN to SOUT Update Mode : From A FF to Port Out
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Test Access Port (TAP) Controller
State diagram consist of
1.To control the operation of
data register Select
TMS Capture
2.To control the operation of
instruction register Shift
3.The controller changes the TAP
TCK Exit
state only when a clock pulse Controller
on TCK occurs Pause
4.The next state is determined
by logic level of line TMS Update

Select : Scan data sequence is initiated

Capture : Data is loaded into data test register
Shift : 1 bit shift
Exit : Test data registers hold their own state
Pause : Temporarily hold the scan operation allowing master to reload data
Update : Test data register is loaded from associated shift register

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1 Test logic reset
1 1
0 1 Select IR-Scan
Select DR-Scan
0 Run test/ idle
0 0
Capture-DR 1 Capture-IR
1
0 0
0 Shift-IR 0
Shift-DR
1 1

Exit-DR Exit-IR
1
1 0
0
Pause-DR Pause-IR
0 0
1 1
0 0
Exit 2-DR Exit 2-IR

1 1

Update-DR Update-IR
1 1
0
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Thank you !!!!

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