CS321 Computer Architecture
CS321 Computer Architecture
Bus 8 Bit
MUX
ACC tmp R
IR W Z
B C
Flag
I Decode D E
& H L
M/C
ALU Encodin
SP
g PC
Inc/Dec. ter
Add latch
Memory I/P
8085
MPU
O/P
D7
Data Bus (8bit)
D0
• HLDA: Hold Acknowledge: Indicates that the CPU has received the
HOLD request and that it will relinquish the bus in the next clock cycle.
– HLDA goes low after the Hold request is removed. The CPU takes the bus one
half-clock cycle after HLDA goes low.
Ready Signal
• READY: This signal Synchronizes the fast CPU and the
slow memory, peripherals.
• If READY is high during a read or write cycle, it
indicates that the memory or peripheral is ready to
send or receive data.
• If READY is low, the CPU will wait an integral number
of clock cycle for READY to go high before completing
the read or write cycle.
• READY must conform to specified setup and hold
times.
Interrupts
• 8085 has 5 interrupts priority (from lowest to highest):
• INTR: (maskable and non-vectored interrupt). When the interrupt occurs, the processor fetches from the bus
one instruction, usually one of these instructions:
– One of the 8 RST instructions (RST0 - RST7). The processor saves current program counter into stack and branches to
memory location N * 8 (where N is a 3-bit number from 0 to 7 supplied with the RST instruction).
– CALL: (3 byte instruction). The processor calls the subroutine, address of which is specified in the second and third bytes of
the instruction.
• RST5.5: (maskable interrupt). When this interrupt is received the processor saves the contents of the PC
register into stack and branches to 2CH address.
• RST6.5: (maskable interrupt) When this interrupt is received the processor saves the contents of the PC
register into stack and branches to 34H address
• RST7.5 (maskable interrupt) When this interrupt is received the processor saves the contents of the PC
register into stack and branches to 3CH (hexadecimal) address
• TRAP: (non-maskable interrupt) When this interrupt is received the processor saves the contents of the PC
register into stack and branches to 24H address.
• All maskable interrupts can be enabled or disabled using EI and DI instructions. RST 5.5, RST6.5 and RST7.5
interrupts can be enabled or disabled individually using SIM instruction
8085 Non-Vectored Interrupt Process
• The interrupt process should be enabled using the EI instruction.
• The 8085 checks for an interrupt during the execution of every instruction.
• If INTR is high, Processor completes current instruction, disables the interrupt
and sends INTA (Interrupt acknowledge) signal to the device that interrupted
• INTA allows the I/O device to send a RST instruction through data bus.
• MP saves the memory location of the next instruction, on the stack and the
program is transferred to ‘call’ location (ISR Call) specified by the RST instruction
• Microprocessor Performs the ISR. ISR must include the ‘EI’ instruction to enable
the further interrupt within the program.
• RET instruction at the end of the ISR allows the MP to retrieve the return
address from the stack and the program is transferred back to where the
program was interrupted.
Interrupt vectors
• An interrupt vector is a pointer to where the ISR is stored in
memory.
• All interrupts (vectored or otherwise) are mapped onto a memory
area called the Interrupt Vector Table(IVT).
• The IVT is usually located in memory page 00 (0000H - 00FFH).
• Example:
– Let a device interrupts the Microprocessor using the RST 7.5 interrupt line.
– Because the RST 7.5 interrupt is vectored, Microprocessor knows in which
memory location it has to go using a call instruction to get the ISR address.
– RST7.5 is known as Call 003Ch to Microprocessor. Microprocessor goes to
003C location and will get a JMP instruction to the actual ISR address. The
microprocessor will then, jump to the ISR location
Vectored Interrupt
• The interrupt process should be enabled using the EI instruction.
• The 8085 checks for an interrupt during the execution of every
instruction.
• If there is an interrupt, and if the interrupt is enabled using the
interrupt mask, the microprocessor will complete the executing
instruction, and reset the interrupt flip flop.
• The microprocessor then executes a call instruction that sends the
execution to the appropriate location in the interrupt vector table.
• When the microprocessor executes the call instruction, it saves the
address of the next instruction on the stack.
• The microprocessor jumps to the specific service routine.
• The service routine must include the instruction EI to re-enable the
interrupt process.
• At the end of the service routine, the RET instruction returns the
execution to where the program was interrupted.
MANIPULATING THE MASKS
– The individual masks for RST 5.5, RST 6.5 and RST 7.5
are manipulated using the SIM instruction.
M7.5
M5.5
M6.5
MSE
SDO
R7.5
SDE
XXX
}
RST5.5 Mask
Serial Data Out 0 - Available
RST6.5 Mask
1 - Masked
RST7.5 Mask
If MSE is 1
If the mask bit is 0, the interrupt is available.
If the mask bit is 1, the interrupt is masked.
23
How RIM sets the Accumulator’s different bits
7 6 5 4 3 2 1 0
M7.5
M5.5
M6.5
P6.5
P7.5
P5.5
SDI
IE
}
RST5.5 Mask
Serial Data In 0 - Available
RST6.5 Mask
1 - Masked
RST7.5 Mask
RST5.5 Interrupt Pending
RST6.5 Interrupt Pending
RST7.5 Interrupt Pending Interrupt Enable
Value of the Interrupt Enable
Flip Flop
Determining the Current Mask Settings
• RIM instruction: Read Interrupt Mask
– Load the accumulator with an 8-bit pattern showing the status of each interrupt pin and
mask.
RST7.5 Memory
RST 7.5
M 7.5
7 6 5 4 3 2 1 0
M5.5
M7.5
M6.5
P7.5
P6.5
P5.5
SDI
IE
RST 6.5
M 6.5
RST 5.5
M 5.5
Interrupt Enable
Flip Flop
25
What is Memory Mapped I/O?
• Instead of having special methods for accessing
the values to be read or written, just get them
from memory or put them into memory.
• The device is connected directly to certain main
memory locations.
• Two types of information to/from the device
– Status
– Value read/write
Memory Mapped I/O
CPU
Address
Data
7 0
Main memory
Data register
(address = 5000)
7 0
Keyboard controller
Mother Board
comparison
Memory mapping I/O mapping
16/20 bit address are provided for I/O devices 8-bit or 16-bit addresses are provided for I/O
devices
The I/O ports or peripherals can be treated like Only IN and OUT instructions can be used for data
memory locations and so all instructions related transfer between I/O device and processor
to memory can be used for data transmission
between I/O device and processor
Data can be moved from any register to ports Data transfer takes place only between
and vice versa accumulator and ports
When memory mapping is used for I/O devices, Full memory space can be used for addressing
full memory address space cannot be used for memory.
addressing memory.
Suitable for systems which require large
Useful only for small systems where memory memory capacity
requirement is less
For accessing the memory mapped devices, the For accessing the I/O mapped devices, the
processor executes memory read or write cycle. processor executes I/O read or write cycle.
• Addressing mode
– Register - references the data in a register or in a register pair.
– Register indirect - instruction specifies register pair containing address, where the data is
located.
– Direct,
– Immediate - 8 or 16-bit data
8085 Microprocessor Memory
• Memory:
Program, data and stack memories occupy the same memory space. The total
addressable memory size is 64KB.
• Data memory - the processor always uses 16-bit addresses so that data can be
placed anywhere.
• Stack memory is limited only by the size of memory. Stack grows downward.
• First 64 bytes in a zero memory page should be reserved for vectors used by RST
instructions
8085 MP Instruction Set Architecture
• Contains several registers include B,C,D,E,H,L and an 8-bit
accumulator register, A.
• The registers B,C,D,E,H,L can be accessed as pairs. Pairs are not
arbitrary. B and C, D and E, H and L.
• SP is a 16 bit stack pointer register pointing to the top of the stack.
• PC is a 16-bit Program counter
• Contains five flags known as flag registers:
Instruction Set of 8085
• Arithmetic Operations
– add, sub, inr/dcr
• Logical operation
– and, or, xor, rotate, compare, complement
• Branch operation
– Jump, call, return
• Data transfer/Copy/Memory operation/IO
– MOV, MVI, LD, ST, OUT
Copy/Mem/IO operation
• MVI R, 8 bit // load immediate data
• MOV R1, R2 // Example MOV B, A
• MOV R M // Copy to R from 0(HL Reg) Mem
• MOV M R // Copy from R to 0(HL Reg) Mem
• INR R // R = R+1
• INR M // 0(HL)=0(HL)+1
• DCR R // R = R-1
• DCR M // 0(HL)=0(HL)-1
• INX Rp // Rp=Rp+1
• DCX Rp // Rp=Rp-1
Other Operations
• Logic operations
– ANA R ANI 8bit ANA M
– ORA, ORI, XRA, XRI
– CMP R // compare with R with ACC
– CPI 8bit // compare 8 bit with ACC
• Branch operations
– JMP 16bit, CALL 16 bit
– JZ 16bit, JNZ 16bit, JC 16bit, JNC 16 bit
– RET
• Machine Control operations
– HLT, NOP, POP, PUSH
8085 Microprocessor Instruction Set
LDA n
i=n
MOV B, A
XRA A sum = A A = 0
Loop: ADD B sum = sum + i
DCR B i=i-1
JNZ Loop IF i 0 THEN GOTO Loop
LDA n B=5
MOV B, A
XRA A A= 0
ADD B A= 5 A= 9 A = 12 A = 14 A = 15
DCR B B = 4, B = 3, B = 2, B = 1, B = 0,
Z=0 Z=0 Z=0 Z=0 Z=1
JNZ Loop JUMP JUMP JUMP JUMP NO JUMP
61
62
Next…
• 8086
– Block diagram (Data Path), Registers
• Memory Model
– Stack, Data and Code Segment
• Instruction Set of x86
• Addressing mode
• Procedure and subroutine
• Examples programs in C/C++ assembly
• Peripheral device and Assembly program
8086 Architecture
Bus Interface
C BUS
Unit
SUM Q6
Q5
Q4
Q3
Q2
Q1
p=(int*)malloc(10); Data
}
Code
Memory layout of C program
• Stack
– automatic (default), local Stack
– Initialized/uninitialized
• Data
Heap
– Global, static, extern
– BSS: Block Started by Symbol BSS
• Code
– program instructions Data
• Heap
– malloc, calloc
Code
8086
Microprocessor Architecture
segments Operating
max = mov AX, [0]
are separate System
j mov BX, [2] and both
(Kernel)
assumed
else cmp AX,BX to start 0700
max = from 0
jle 0x7 //Label_1 Other User
k Every Memory
Process
mov [4], AX Data
Access should
add 0900
jmp 0x5 //Label_2
the value stored
in Our Code
Label_1: mov [4], BX Data Segment
Register Segment
By default.
Label_2: ….
Segment Register 1900
(Data) Vacant
Data Segment: 2100
Address of j: Space
2100 0: // Allocated for j 2100
Address of k:
2102 2: // Allocated for k Our Data
Address of max:
2104
Segment
4: // Allocated for 2300
max Vacant
Space
2500
Ease Of Programming
Main Memory
0000
if (j>k) Code_Segment:
max = j mov AX, [0]
Operating System
else (Kernel)
mov BX, [4]
max = k
cmp AX,BX 0700
2102
Address of 2: // Allocated for k Our
Vacant
Data
2160
max: 2104 Segment
Space
Vacant Space
4: // Allocated for max 2300
Address of j:
Our
Vacant
Data
2300
Segment
Space
Address of k:
2302 2500
Address of Process Mobility
max: 2304
Multiple Segments
mov [ES:10], ax
-this will move the contents
of ax register to memory 1500
location 3510 CS
Opcode
3500
ES
Multiple Segments
Process 1
CS
CS
Process 1
DS
Process 1 in
Execution Process 2
DS
CS
Process 2
SS
SS Process 2
DS
Process 2
in Process 1
SS
Execution
Three Features
Code Mobility
Logically every segment can start
with zero
Inter and Intra process protection
ensuring data integrity.
Real Mode - Memory Addressing
500
CS
Every segment is specified a
1000 start address and limit.
SS 2000
jmpmov
PUSH[ES:499],
CS:501 AX //Let
//This AXSP
is //This
a be 499,
violation is a as
POP
PUSH
movAX
jmp
POPAX //Let
CS:250
[ES:498],
AX//Let
//Let SP
SP
SPbe
AX be
be0,
//This Violation!!!
is itfine
//This
498,
2, it
is
isis
fine
fine
fine
violation!!!
violation
limit is 500
Dedicated Adder to
generate 20 bit address
80
8086
Architecture Bus Interface Unit (BIU)
Microprocessor
81
8086
Architecture Bus Interface Unit (BIU)
Microprocessor
82
8086
Architecture Bus Interface Unit (BIU)
Microprocessor
83
8086
Architecture Bus Interface Unit (BIU)
Microprocessor
84
8086
Architecture Bus Interface Unit (BIU)
Microprocessor
Instruction queue
A group of First-In-First-
Out (FIFO) in which up to
6 bytes of instruction
code are pre fetched
from the memory ahead
of time.
85
8086
Architecture Execution Unit (EU)
Microprocessor
EU decodes and
executes instructions.
A decoder in the EU
control system
translates instructions.
and
Some of the 16 bit registers can be
Index registers (Source used as two 8 bit registers as :
Index, Destination Index)
each of 16-bits AX can be used as AH and AL
BX can be used as BH and BL
CX can be used as CH and CL 86
DX can be used as DH and DL
8086
Architecture Execution Unit (EU)
Microprocessor
87
8086
Architecture Execution Unit (EU)
Microprocessor
88
8086
Architecture Execution Unit (EU)
Microprocessor
Example:
89
8086
Architecture Execution Unit (EU)
Microprocessor
90
8086
Architecture Execution Unit (EU)
Microprocessor
91
8086
Architecture Execution Unit (EU)
Microprocessor
92
8086
Architecture Execution Unit (EU)
Microprocessor
93
8086
Architecture Execution Unit (EU)
Microprocessor
Auxiliary Carry Flag
Carry Flag
Flag Register This is set, if there is a carry from the
This flag is set, when there is
lowest nibble, i.e, bit three during
addition, or borrow for the lowest a carry out of MSB in case of
nibble, i.e, bit three, during addition or a borrow in case
subtraction. of subtraction.
This flag is set, when the This flag is set, if the result of This flag is set to 1, if the lower
result of any computation the computation or comparison byte of the result contains even
is negative performed by an instruction is number of 1’s ; for odd number
zero of 1’s set to zero.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OF DF IF TF SF ZF AF PF CF
Trap Flag
Over flow Flag If this flag is set, the processor
This flag is set, if an overflow occurs, i.e, if the result of a signed enters the single step execution
operation is large enough to accommodate in a destination
mode by generating internal
register. The result is of more than 7-bits in size in case of 8-bit
signed operation and more than 15-bits in size in case of 16-bit interrupts after the execution of
sign operations, then the overflow will be set. each instruction
8086 registers
categorized 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
groups OF DF IF TF SF ZF AF PF CF
Program
A set of instructions written to solve
a problem.
Instruction
Directions which a microprocessor
follows to execute a task or part of a
task.
Computer language
1. Register Addressing
Group I : Addressing modes for
2. Immediate Addressing register and immediate data
3. Direct Addressing
5. Based Addressing
Group II : Addressing modes for
6. Indexed Addressing memory data
7. Based Index Addressing
8. String Addressing
8. String Addressing
101
8086 Group I : Addressing modes for
Microprocessor Addressing Modes register and immediate data
1. Register Addressing
In immediate addressing mode, an 8-bit or 16-bit
2. Immediate Addressing data is specified as part of the instruction
3. Direct Addressing
Example:
4. Register Indirect Addressing
MOV DL, 08H
5. Based Addressing
The 8-bit data (08H) given in the instruction is
6. Indexed Addressing moved to DL
8. String Addressing
10. Indirect I/O port Addressing The 16-bit data (0A9FH) given in the instruction is
moved to AX register
11. Relative Addressing
(AX) 0A9FH
12. Implied Addressing
102
8086
Microprocessor Addressing Modes : Memory Access
1. Register Addressing
2. Immediate Addressing
Here, the effective address of the memory
3. Direct Addressing
location at which the data operand is stored is
4. Register Indirect Addressing given in the instruction.
12. Implied Addressing This addressing mode is called direct because the
displacement of the operand from the segment
base is specified directly in the instruction.
106
8086 Group II : Addressing modes
Microprocessor Addressing Modes for memory data
(CL) (MA)
(CH) (MA +1)
107
8086 Group II : Addressing modes
Microprocessor Addressing Modes for memory data
(CL) (MA)
(CH) (MA + 1)
109
8086 Group II : Addressing modes
Microprocessor Addressing Modes for memory data
110
8086 Group II : Addressing modes
Microprocessor Addressing Modes for memory data
1. Register Addressing
2. Immediate Addressing
1. Register Addressing
2. Immediate Addressing
3. Direct Addressing
5. Based Addressing
6. Indexed Addressing
Instructions using this mode have no operands.
The instruction itself will specify the data to be
7. Based Index Addressing
operated by the instruction.
8. String Addressing
Example: CLC
9. Direct I/O port Addressing
This clears the carry flag to zero.
10. Indirect I/O port Addressing
114
INSTRUCTION SET
8086
Microprocessor Instruction Set
2. Arithmetic Instructions
3. Logical Instructions
116
8086
Microprocessor Instruction Set
117
8086
Microprocessor Instruction Set
118
8086
Microprocessor Instruction Set
120
8086
Microprocessor Instruction Set
2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…
ADD A, data
121
8086
Microprocessor Instruction Set
2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…
ADC A, data
122
8086
Microprocessor Instruction Set
2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…
SUB A, data
123
8086
Microprocessor Instruction Set
2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…
SBB A, data
124
8086
Microprocessor Instruction Set
2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…
125
8086
Microprocessor Instruction Set
2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…
126
8086
Microprocessor Instruction Set
2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…
127
8086
Microprocessor Instruction Set
2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…
128
8086
Microprocessor Instruction Set
2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…
129
8086
Microprocessor Instruction Set
2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…
130
8086
Microprocessor Instruction Set
2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…
CMP A, data
131
8086
Microprocessor Instruction Set
3. Logical Instructions
Mnemonics: AND, OR, XOR, TEST, SHR, SHL, RCR, RCL …
132
8086
Microprocessor Instruction Set
3. Logical Instructions
Mnemonics: AND, OR, XOR, TEST, SHR, SHL, RCR, RCL …
133
8086
Microprocessor Instruction Set
3. Logical Instructions
Mnemonics: AND, OR, XOR, TEST, SHR, SHL, RCR, RCL …
134
8086
Microprocessor Instruction Set
3. Logical Instructions
Mnemonics: AND, OR, XOR, TEST, SHR, SHL, RCR, RCL …
135
8086
Microprocessor Instruction Set
3. Logical Instructions
Mnemonics: AND, OR, XOR, TEST, SHR, SHL, RCR, RCL …
136
8086
Microprocessor Instruction Set
3. Logical Instructions
Mnemonics: AND, OR, XOR, TEST, SHR, SHL, RCR, RCL …
137
8086
Microprocessor Instruction Set
3. Logical Instructions
Mnemonics: AND, OR, XOR, TEST, SHR, SHL, RCR, RCL …
138
8086
Microprocessor Instruction Set
3. Logical Instructions
Mnemonics: AND, OR, XOR, TEST, SHR, SHL, RCR, RCL …
139
8086
Microprocessor Instruction Set
140
8086
Microprocessor Instruction Set
REP
141
8086
Microprocessor Instruction Set
MOVS
(MAE) (MA)
CMPS
SCASW
MAE = (ES) x 1610 + (DI)
Modify flags (AL) - (MAE)
LODS
145
8086
Microprocessor Instruction Set
STOS
146
8086
Microprocessor Instruction Set
CLC Clear CF 0
NOP No operation
Mnemonics Explanation
CALL reg/ mem/ disp16 Call subroutine
148
8086
Microprocessor Instruction Set
Checks flags
149
8086
Microprocessor Instruction Set
Mnemonics Explanation
JC disp8 Jump if CF = 1
JP disp8 Jump if PF = 1
JO disp8 Jump if OF = 1
JS disp8 Jump if SF = 1
151
Assembler directives
8086
Microprocessor Assemble Directives
Used to :
› specify the start and end of a program
› attach value to variables
› allocate storage locations to input/ output data
› define start and end of segments, procedures, macros etc..
153
8086
Microprocessor Assemble Directives
DB Define Byte
PROC
FAR Example:
NEAR LIST DB 7FH, 42H, 35H
ENDP
Three consecutive memory locations are reserved for
SHORT the variable LIST and each data specified in the
instruction are stored as initial value in the reserved
MACRO memory location
ENDM 154
8086
Microprocessor Assemble Directives
DB Define Word
PROC
FAR Example:
NEAR ALIST DW 6512H, 0F251H, 0CDE2H
ENDP
Six consecutive memory locations are reserved for
SHORT the variable ALIST and each 16-bit data specified in
the instruction is stored in two consecutive memory
MACRO location.
ENDM 155
8086
Microprocessor Assemble Directives
ORG
END Segnam SEGMENT
EVEN
…
EQU … Program code
… or
PROC … Data Defining Statements
…
FAR …
NEAR
ENDP Segnam ENDS
SHORT
ORG
User defined name of
END Segment Register
the segment
EVEN
EQU
PROC Example:
FAR
NEAR ASSUME CS: ACODE, DS:ADATA Tells the compiler that the
ENDP instructions of the program are
stored in the segment ACODE and
data are stored in the segment
SHORT ADATA
MACRO
ENDM 157
8086
Microprocessor Assemble Directives
General form
ASSUME
ORG
procname PROC[NEAR/ FAR]
END
EVEN …
Program statements of the
EQU …
procedure
…
DB
Examples:
DW
ORG RET
ADD64 ENDP
END
EVEN
EQU CONVERT PROC FAR The subroutine/ procedure named CONVERT
is declared as FAR and so the assembler will
… code the CALL and RET instructions involved
PROC … in this procedure as far call and return
ENDP …
FAR
RET
NEAR
CONVERT ENDP
SHORT
MACRO
ENDM 160
8086
Microprocessor Assemble Directives
PROC
ENDP
FAR
NEAR
SHORT
MACRO
ENDM 161
8086
Microprocessor Assemble Directives
PROC
ENDP
FAR User defined name of
NEAR the macro
SHORT
MACRO
ENDM 162