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    STA Temp

    Uploaded by

    Nivin Paul
    This document outlines various techniques for robust verification including: 1. Modeling on-chip variation to account for local process variations. 2. Analyzing timing with time borrowing techniques like cycle stealing. 3. Performing data-to-data and non-sequential checks between related logic cells. 4. Inferring and specifying clock gating checks between clock and gating signals. 5. Managing power through techniques like clock gating, power gating, multi-threshold voltage cells, and well biasing.

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    STA Temp

    Uploaded by

    Nivin Paul
    174 views34 pages
    This document outlines various techniques for robust verification including: 1. Modeling on-chip variation to account for local process variations. 2. Analyzing timing with time borrowing techniques like cycle stealing. 3. Performing data-to-data and non-sequential checks between related logic cells. 4. Inferring and specifying clock gating checks between clock and gating signals. 5. Managing power through techniques like clock gating, power gating, multi-threshold voltage cells, and well biasing.

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    STA

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    STA-temp

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    This document outlines various techniques for robust verification including: 1. Modeling on-chip variation to account for local process variations. 2. Analyzing timing with time borrowing techniques like cycle stealing. 3. Performing data-to-data and non-sequential checks between related logic cells. 4. Inferring and specifying clock gating checks between clock and gating signals. 5. Managing power through techniques like clock gating, power gating, multi-threshold voltage cells, and well biasing.

    Copyright:

    © All Rights Reserved
    Download as PPTX, PDF, TXT or read online from Scribd
    Download as pptx, pdf, or txt
    174 views34 pages

    STA Temp

    Uploaded by

    Nivin Paul
    This document outlines various techniques for robust verification including: 1. Modeling on-chip variation to account for local process variations. 2. Analyzing timing with time borrowing techniques like cycle stealing. 3. Performing data-to-data and non-sequential checks between related logic cells. 4. Inferring and specifying clock gating checks between clock and gating signals. 5. Managing power through techniques like clock gating, power gating, multi-threshold voltage cells, and well biasing.

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    Robust verification

    Outline
    1. On chip variation
    2. Time borrowing
    3. Data to data checks
    4. Non sequential checks
    5. Clock gating checks
    6. Power management
    7. Back annotation
    8. Sign off methodology
    9. Statistical STA
    10. Debugging STA results
    11. Validating Timing Constraints
    On chip variation
    Bold

    OCV, CPP, CRPR,


    Analysis with OCV at worst PVT condition
    OCV for hold clocks
    Analysis with OCV at best PVT condition
    OCV
    Process as in PVT is about variation in different chips (across multiple manufacturing lots)
    OCV => variation in same chip/die

    OCV => local process variation.


    Variation across lots => global process variation (slow to fast)

    Local variations are smaller compared to global

    Apart from process, different regions in die can see different voltage and temp:
    1. IR drop affecting local pwer supply
    2. Voltage threshold variation
    3. Channel length variation
    4. Local temp hot spots
    5. Variations in metal etch, thickness
    How to model OCV?
    STA can include OCV effects by derating derating delays of
    specific paths. Make paths faster or slower by derating
    cell/wire delays
    Time borrowing
    Bold
    Cycle stealing, opening edge, closing edge
    Example with no time borrowed
    Example with time borrowed
    Example with timing violation
    Look more
    Latch based designs are used in high peed designs.

    http://mantravlsi.blogspot.com/2014/07/time-borrowing-and-
    time-stealing.html

    https://www.eetimes.com/document.asp?doc_id=1278980

    http://ohotspot.blogspot.com/2012/09/time-borrowing-and-
    time-stealing.html
    Data to Data Checks
    Bold
    Constrained pin, related pin, zero-cycle checks, same-cycle
    checks

    set_data_check
    Non sequential checks
    Bold
    Non sequential setup check
    Non sequential hold check
    Non sequential check is similar to data to data check EXCEPT:
    1. These checks are applied to cells or macros. This is specified as part of cell
    library. No specific command to do the check in STA. Data to data check can
    be applied to pins in a design.
    2. Setup and hold values are obtained from cell libraries. This is not a fixed
    value. It can come from a non linear delay model (NLDM). We can specify
    only a single value for data to data check.

    1. One pin acts like data, another pin like clock


    2. Constrained pin => data
    3. Related pin => clock
    pin (WEN) { Setup rising : rising edge of related pin
    timing () { Intrinsic setup rise: Rise setup time
    timing_type: non_seq_setup_rising; Intrinsic setup fall: Fall setup time
    intrinsic_rise: 1.1;
    intrinsic_fall:1.15; Similar timing arcs for hold_rising,
    related_pin: “D0”; setup_falling and hold_falling
    }
    timing () {
    timing_type: non_seq_hold_rising;
    intrinsic_rise: 0.6;
    intrinsic_fall:0.65;
    related_pin: “D0”;
    }
    }
    Violation will occur when WEN
    changes in setup+hold window.
    Clock gating checks
    Bold
    Clock pin, gating pin, gating cell, set_clock_gating_check
    Active high clock gating
    Active low clock gating
    Clock gating with a multiplexer
    Clock gating with clock inversion
    Gating cell: logic cell where gating
    occurs
    Clock pin: pin of gating cell
    connected to clock
    Gating pin: pin of gating cell
    connected to gating signal
    Two conditions for inferring clock gating
    check
    1. Gated clock should be should as clock downstream. It can be
    1. Clock for FF
    2. Fanout to output port
    3. Generated clock which refers the output of cell as master

    2. Gating pin should not be used as clock downstream

    Gating block need not be a single cell but can be a logic block. For
    clock gating to be inferred, gating and clock pin should fanout to one
    output pin
    Active high and Active low
    Logic state of gating signal which activates the clock at output of gating cell.

    There are two types of clock gating checks inferred:


    • Active-high clock gating check: Occurs when the gating cell has an and or a nand function.
    • Active-low clock gating check: Occurs when the gating cell has an or or a nor function

    Sometimes, it can be complex function: mux or xor. STA


    may not infer gating check. Check can be specified
    explicitly using set_clock_gating_check
    Active high
    Gating signal should not create a
    active edge on fanout clock.

    Pos edge trigger: rising edge of


    gating signal when clock is low.

    Neg edge trigger: falling edge of


    gating signal when clock is low.

    Above two conditions are the


    reason for setup and hold check.
    Setup report
    Hold report
    Hold check fails!!
    Hold violation since the gating signal changes during the
    positive cycle of clock.

    Adding 5ns b/w Q and AND gate fixes hold. Hold time
    requierement is large here.

    We can reduce this by using a negative edge triggered


    flop to generate the gating signal.
    Active low clock gating
    Clock gating with multiplexer
    STA may not infer clock gating if the logic
    is complex.

    Assume, TCLK is low.

    Gating signal has to change when MCLK


    is low => Active high gating.

    Clock gating check forced with :


    Set_clock_gating_check
    Setup check: gating signal stable at active edge of clock
    Setup violation: Glitch at fanout clock
    Hold check: gating signal stable at inactive edge of clock.

    Gotcha: For setup, consider the active edge after the data transition. If the next edge
    is inactive edge, go to the active edge after it.
    For hold, consider the inactive edge preceding data change. If it is active consider the
    inactive edge after data change---Violation!!
    Power management
    Bold
    Minimize total active power of the design
    Minimize the power dissipation of design in standby mode
    Clock gating, power gating, Multi Vt cells, Well bias

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