NATIONAL INSTITUTE OF TECHNOLOGY SILCHAR

VLSI Design

Dr. T. R. Lenka
Asst. Professor, Dept. of ECE

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Outline
• Introduction to VLSI Design
 Historical Perspective
 Moore’s Law
 Evolution of Microelectronics

• VLSI Design Methodology

• Programmable Logic Devices

• Standard Digital ICs

 VLSI (Very Large Scale Integration)
Computation
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Transport
Computation
Military Military
Communication
Transport
Physics Industrial
Space Consumer
Chemistry Electronics
Entertainment
Material Very Large Subjects Integration
Economics
Health Electronics
Communication Mathematics
……….. Computer
science
Very Large Application Integration
Biology
Language
……. Courtesy: Dr. S C Bose, CEERI, Pilani

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Periodic Table
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History of IC
 The First Transistor
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First transistor on Ge
Bell Labs, 1947-1948
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Inventor of First IC

Jack Kilby
1923 - 2005
Texas Instruments
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Founder of Intel Inc.

Sir Gordon Moore
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Moore’s Law

In 1965, Gordon Moore noted that the

density of transistors on a chip doubles every
24 months.

In1980 he made another prediction that the
density of transistors on a chip will be
doubled in every 18 months.

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LOG2 OF THE NUMBER OF

COMPONENTS PER INTEGRATED FUNCTION

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1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

1959
1960
1961
1962

Electronics, April 19, 1965.

1963
1964
1965

VLSI Design
1966
1967
1968
1969
1970
Moore’s Law

1971
1972
1973
1974
1975
10
 Moore's first law: transistors integrated on a single chip
(Commercial Products)
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Number of transistors per chip (Complexity)

1.0E+09

1.0E+08 Predicted
1.0E+07

1.0E+06

1.0E+05

1.0E+04

1.0E+03

1.0E+02

1.0E+01

1.0E+00
1960 1965 1970 1975 1980 1985 1990 1995 2000 2006
Year
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 The First Computer
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The Babbage
Difference Engine
(1832)
25,000 parts
cost: £17,470

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 ENIAC - First Electronic Computer (1946)
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The First Integrated Circuit

Bipolar
logic
1960’s

ECL 3-input Gate

Motorola 1966

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Evolution of Microelectronics

1948 1961 1966 1971 1980

Discrete SSI MSI LSI VLSI
Component

1 100 100-1000 1000-20000 >20000

transistor
Gates, Counters, 8-bit uP, ROM, Complex
FFs MUX, RAM uP, SoC
Adders

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Evolution of Microelectronics
Microelectronics evolution
Year 1947 1950 1961 1966 1971 1980 1990 2000
Invention
of the Discrete
Technology transistor Components SSI MSI LSI VLSI ULSI GSI
Approximat
e number of
transistors
per chip in
Commercial 1000- 20,000- 1,000,000-
Products 1 1 10 100-1000 20,000 1,000,000 10,000,000 >10,000,000
Special
Processors
Planar 16 and 32 bit Virtual
devices, mp Reality
Junction, Logic Counters 8-bit mp Sophisticated Machines
Typical Transistor gates, Flip Multiplex ROM peripherals Smart
Products - and diode Flops Adders RAM Dram Sensors

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Four Decades of IC’s

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Battery Industry does not have

a Gordon Moore
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 Propagation Delay
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10ns

nMOS
1ns
CMOS

BiCMOS
ECL

100ps
GaAs

10ps Power dissipation/gate

10µW 100µW 1mW 10mW 100mW

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 Microelectronics
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Inert Substrate Active Substrate

Thick Thin
film film Silicon GaAs

MOS MESFET Bipolar

Bipolar
NMOS CMOS
TTL ECL
PMOS
Bi-CMOS Many Linear

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Industry Trends

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VLSI Applications
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Intel 4004 Micro-Processor

1971
1000 transistors
1 MHz operation

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Intel Pentium (IV) Microprocessor

2002
42 million
transistors
3GHz operation
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ULSI and SOC
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0.18µ VLSI Technology

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0.13µ VLSI Technology

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0.13µ VLSI Technology

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Challenges:
How to cope with Design
Complexity?
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As Technology Scaled Down…..

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 Evolution in Complexity
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 Transistor Counts
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1 Billion
K Transistors
1,000,000
100,000
Pentium® III
10,000 Pentium® II
Pentium® Pro
1,000 Pentium®
i486
100 i386
80286
10 8086
Source: Intel
1
1975 1980 1985 1990 1995 2000 2005 2010 2015
Courtesy, Intel
Projected
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 Moore’s law in Microprocessors
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Transistors on Lead Microprocessors double every 2 years

1000

100 2X growth in 1.96 years!

Transistors (MT)

10
P6
Pentium® proc
1 486
386
0.1 286
8085 8086
0.01 8080
8008
4004
0.001
1970 1980 1990 2000 2010
Year
Courtesy, Intel

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Die Size Growth
100
Die size (mm)

P6
486 Pentium ® proc
10 386
286
8080 8086
8085 ~7% growth per year
8008
4004 ~2X growth in 10 years

1
1970 1980 1990 2000 2010
Year Courtesy, Intel

Die size grows by 14% to satisfy Moore’s Law

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Frequency
10000
Doubles every
1000
2 years
Frequency (Mhz)

P6
100
Pentium ® proc
486
10 8085 386
8086 286

1 8080
8008
4004
0.1
1970 1980 1990 2000 2010
Year Courtesy, Intel

Lead Microprocessors frequency doubles every 2 years

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Power Dissipation
100

P6
Pentium ® proc
Power (Watts)

10
486
8086 286
386
8085
1 8080
8008
4004

0.1
1971 1974 1978 1985 1992 2000
Year Courtesy, Intel

Lead Microprocessors power continues to increase

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Power- a major Problem
100000
18KW
10000 5KW
1.5KW
Power (Watts)

1000 500W
Pentium® proc
100
286 486
10 8086 386
8085
8080
8008
1 4004

0.1
1971 1974 1978 1985 1992 2000 2004 2008
Year Courtesy, Intel

Power delivery and dissipation will be prohibitive

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Power Density
10000
Rocket
Power Density (W/cm2)

Nozzle
1000
Nuclear
Reactor
100

8086
10 4004 Hot Plate P6
8008 8085 386 Pentium® proc
286 486
8080
1
1970 1980 1990 2000 2010
Year Courtesy, Intel

Power density too high to keep junctions at low temp

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Not Only Microprocessors

Cell
Phone

Small Power
Signal RF RF

Digital Cellular Market

(Phones Shipped)
Power
Management
1996 1997 1998 1999 2000
Units 48M 86M 162M 260M 435M Analog
Baseband

Digital Baseband
(DSP + MCU)
(Data from Texas Instruments)

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Challenges in VLSI Design
“Microscopic Problems” “Macroscopic Issues”

• Ultra-high speed design • Time-to-Market

• Interconnect • Millions of Gates
• Noise • High-Level Abstractions
• Reliability, Manufacturability • Reuse : Portability
• Power Dissipation • Predictability.
• Clock distribution.
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Why Scaling?
• Technology shrinks by 0.7/generation.
• With every generation can integrate 2x
more functions per chip; chip cost does
not increase significantly.
• Cost of a function decreases by 2x.
• But …
– How to design chips with more and more
functions?
– Design Engineers do not double every two
years…
• Hence, a need for more efficient design
methods
– Exploit different levels of abstraction
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Design Abstraction Levels
SYSTEM

MODULE
+

GATE

CIRCUIT

DEVICE
G
S D
n+ n+

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Design Metrics
• How to evaluate performance of a
digital circuit (gate, block, …)?
Cost
Reliability
Scalability
Speed (delay, operating frequency)
Power dissipation
Energy to perform a function
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Cost of Integrated Circuits
• NRE (Non-Recurrent Engineering)
Costs:
– design time and effort, mask generation
– one-time cost factor
• Recurrent Costs:
– silicon processing, packaging, test
– proportional to volume
– proportional to chip area
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NRE Cost is Increasing

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Wafer Diameter Trends

300 mm

200 mm

150 mm
125 mm
100 mm

75 mm

3 4 5 6 8 12

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Wafer with IC’s
Single die

Wafer

From http://www.amd.com Going up to 12” (30cm)

 Increase in Number of Chips
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on Larger Wafer Diameter

88 die
200-mm wafer
232 die
300-mm wafer
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Wafer Identifying Flats

P-type (111) P-type (100)

N-type (111) N-type (100)

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Cost per Transistor

Cost:
$-per-
Transistor

1
0.1 Fabrication capital cost per transistor (Moore’s law)
0.01
0.001
0.0001
0.00001
0.000001
0.0000001
1982 1985 1988 1991 1994 1997 2000 2003 2006 2009 2012

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IC Chip Packaging
Chip
Bonding
Pad

Pins

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 Top-down view of the Mixed
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Signal IC Design Process

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Typical Chip Cross Section

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As Technology Scaled Down…

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As Technology Scaled Down…..

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Verifying Design is IMPORTANT !!!

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Design Productivity Solutions
 Designs are getting larger and more
complex
- design times are getting shorter
- Fast time-to-market is crucial
 Xilinx / Altera:
It offers design methodologies and well
documented, proven logic cores that
increase productivity and reduce risk.

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Users Expectations
• Logic Capacity
- 50,000 to a million gates
• Clock Speed
- 100 MHz and above
• Cost
- Reasonable premium over ASICs
•Design effort and time
- powerful synthesis, fast compile time
• Power consumption
- must stay within limits

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Why Low Power?
• Longer Battery life:
- A4 size portable multimedia terminal
with off-the-shelf components
dissipates 40W
- NiH batteries (65 watt-hrs./kg.) weigh
6Kg for a 10 hour operation
- Li-ion or Li-Polymer (100watt-hrs/Kg)
weigh 4Kg.

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Why Low Power?
Smaller weight:
Less cooling requirement
Current Microprocessor with 100-200
MHz clock, dissipates 15-30W
Extrapolation: 10 sq.cm. Microprocessor
at 500MHz would dissipate 300W
Reliability
Environmental friendliness

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 Low Power Design Spec.
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•Voltage Control

• Minimizing Capacitance

• Minimizing Switching activity

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Voltage Control
• Scaling VDD:
- Quadratic effect in power
- Minimum VDD =VTh,nMOS+ VTh,pMOS
- Whole Chip scaling: maximum advantage
- Individual Modules: needs voltage converters
- Adaptive Scaling
• Scaling VTh:
- Allows VDD to be scaled without loss of speed
- Limited by noise margin requirements

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Minimizing Capacitance
• Device and Interconnect Capacitance:
- Design Optimizations

• Parasitic Capacitance:
- Process Optimizations

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Minimizing Switching Activity
Minimize amount of useful switching
required

 Minimize Glitches

 Eliminate Clock:
- asynchronous design

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Power Reduction at Various Steps in Design

• Application technology and algorithms

level
• Process Level
• System design level
• Behavioral/RTL synthesis level
• Logic Design level
• Physical Design Level

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Design Alternatives
• Microprocessors
- Ideal, if fast enough
• Gates, MSI, PALs
- Outdated, inefficient, inflexible
• Dedicated Standard Chip Sets
- Cheap, but no product differentiation
• ASIC’s
- Only for rock-stable, high-volume designs

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 ASIC’s: Becoming Less Attractive
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•Non-Recurring Engineering cost increases

- more masking steps
- more expensive masks

• Minimum order quantity rises

- Larger wafers, smaller die

• Silicon capability exceeds user requirement

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 Recent Developments
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•Deep submicron arrived unexpectedly early

--> 0.5 -> 0.35 -> 0.25 -> 0.18 micron

• Deep submicron technology provides

“for free”
- Speed, Density, Low cost

• But it requires voltage migration

-> 5V -> 3.3V -> 2.5V -> 1.8V -> 1.5V -> ?

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 Recent Developments
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• Standard Product Advantages

- Steep learning curve, cost decline
- performance gain, speed binding

• IC manufacturing is best for

mass-production
- Custom devices have an inherent
disadvantage

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“This is the cause for which

ASIC Suppliers
are leaving this
overly competitive market”

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However, Programmable
Logic can be used for…….
- Flexibility and Performance

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FPGAs & Design Softwares

are good enough
- better & better than ASIC’s
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• Adequate Capacity, Performance

-20,000 gates, 85MHz in 1998
-1,00,000 gates, 200MHz in 2005-06

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The Programmable Frontier

Then:1999 In :2006-07
• 250K gates • 1 Million gates
• 100 MHz •170MHz
•$5 •@1.95$ for Spartan XL

Four times bigger and thrice as fast at half

the price in one year

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The Programmable Frontier
8.2i Device Support
all Xilinx leading FPGA/CPLD families
• New leading-edge device families

• ISE advantages can be leveraged across various

Engineering courses
– Across all device families and design sizes

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FPGA’s avoid the risks of ASIC’s

- The Design Risk
- The Time to Market Risk
- The Inventory Risk

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The Compelling Conclusion
Programmable is the way to go!
• FPGA’s provide performance and
flexibility:
- the performance of custom-hardware
- the ease of design and inherent
flexibility of a microprocessor solution

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Is it true that always one

should go for FPGA ????

For the Mass Production ! ! !

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VLSI Design Methodology

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VLSI Design Flow
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VLSI Design Methodology
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VLSI Design Methodology

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VLSI Design Methodology

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VLSI Design Methodology

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VLSI Design Methodology

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VLSI Design Methodology

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VLSI Design Methodology
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VLSI Design Methodology

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VLSI Design Methodology

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VLSI Design Methodology

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VLSI Design Methodology

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VLSI Design Methodology

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VLSI Design Methodology

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VLSI Design Methodology

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VLSI Design Methodology

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VLSI Design Methodology

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VLSI Design Methodology

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VLSI Design Methodology

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VLSI Design Methodology

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VLSI Design Methodology

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VLSI Design Methodology

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VLSI Design Methodology

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VLSI Design Methodology

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VLSI Design Methodology

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VLSI Design Methodology

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VLSI Design Methodology

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VLSI Design Methodology

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HDL based Design
VHSIC Hardware Description Language
One should learn VHDL for IC Design.
Aldec is a good Vendor for VHDL Compiler.

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Aldec-HDL for HDL Design
Features:
• Very good Front-end tool for VHDL/
Mixed-HDL
• No more Schematic design
• Compatible with almost all VLSI tool
• Floating License (no hardware)
• Well compatible with Xilinx Back-end

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VLSI Design Methodology

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VLSI Design Methodology

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VLSI Design Methodology

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VLSI Design Methodology

Use
synthesizer
to generate
the Gate
Level netlist

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VLSI Design Methodology

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VLSI Design Methodology

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VLSI Design Methodology

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VLSI Design Methodology

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VLSI Design Methodology

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Overview of Design Styles

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We must have a
well-defined
VLSI Design Methodology
to handle these
complex problems….

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 FPGA Design Flow
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The Beauty of Tanner Tool

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 Layout of an Inverter
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pMOS

nMOS

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 Layout of 3 input NAND gate
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Electronic design automation (EDA) Tools

OrCAD - Schematic Design

PCAD - PCB Design
PSpice - Analog/Digital/Mixed-Signal
Design
Xilinx - Design, Simulation &
Implementation
ALDEC - VHDL/Verilog Simulator
MicroTec - Process Simulation
Tanner - Schematic & Layout Design
(Achieved Chip)
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For Advanced VLSI Design
Synopsys IC Station

Synopsys/SILVACO TCAD

Cadence IC Station

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Prerequisites!

Electronic Devices
Electronic Circuits
Digital Logic Design

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