Synthesis vs.

Simulation
• Extremely important to understand that SystemVerilog is BOTH
a “Synthesis” language and a “Simulation” language
– Small subset of the language is “synthesizable”, meaning that it
can be translated to logic gates and flip-flops.
– SystemVerilog also includes many features for “simulation” or
“verification”, features that have no meaning in hardware!

• Although SystemVerilog syntactically looks like “C”, it is a

Hardware Description Language (HDL), NOT a software
programming language
– Every line of synthesizable SystemVerilog MUST have a direct
translation into hardware (logic gates and flip flops).
– Very important to think of the hardware that each line of
SystemVerilog will produce.

1
 SystemVerilog Modules
SystemVerilog:
module example(input logic a, b, c,
output logic y);
assign y = ~a & ~b & ~c | a & ~b & ~c | a & ~b & c;
endmodule

Module Abstraction:

a
Verilog
b y
Module
c

Slide derived from slides by Harris & Harris from their book 2
 HDL Synthesis
SystemVerilog:
module example(input logic a, b, c,
output logic y);
assign y = ~a & ~b & ~c | a & ~b & ~c | a & ~b & c;
endmodule

Synthesis: translates into a netlist (i.e., a list of gates and flip-

flops, and their wiring connections)
b
c y

un5_y
y

* Schematic after some

a
logic optimization

un8_y
Slide derived from slides by Harris & Harris from their book 3
 SystemVerilog Syntax
• Case sensitive
– Example: reset and Reset are not the same signal.
• No names that start with numbers
– Example: 2mux is an invalid name
• Whitespace ignored
• Comments:
– // single line comment
– /* multiline
comment */

Slide derived from slides by Harris & Harris from their book 4
 Structural Modeling - Hierarchy
module and3(input logic a, b, c,
output logic y);
assign y = a & b & c;
endmodule

module inv(input logic a,

output logic y);
assign y = ~a;
endmodule

module nand3(input logic a, b, c

output logic y);
logic n1; // internal signal

and3 andgate(a, b, c, n1); // instance of and3

inv inverter(n1, y); // instance of inverter
endmodule

Slide derived from slides by Harris & Harris from their book 5
 Bitwise Operators
module gates(input logic [3:0] a, b,
output logic [3:0] y1, y2, y3, y4, y5);
/* Five different two-input logic
gates acting on 4 bit busses */
assign y1 = a & b; // AND
assign y2 = a | b; // OR
assign y3 = a ^ b; // XOR
assign y4 = ~(a & b); // NAND
assign y5 = ~(a | b); // NOR
endmodule

// single line comment

/*…*/ multiline comment

Slide derived from slides by Harris & Harris from their book 6
 Reduction Operators
module and8(input logic [7:0] a,
output logic y);
assign y = &a;
// &a is much easier to write than
// assign y = a[7] & a[6] & a[5] & a[4] &
// a[3] & a[2] & a[1] & a[0];
endmodule

Slide derived from slides by Harris & Harris from their book 7
 Conditional Assignment
module mux2(input logic [3:0] d0, d1,
input logic s,
output logic [3:0] y);
assign y = s ? d1 : d0;
endmodule

? : is also called a ternary operator because it

operates on 3 inputs: s, d1, and d0.

Slide derived from slides by Harris & Harris from their book 8
 Precedence
Order of operations
Highest ~ NOT
*, /, % mult, div, mod
+, - add,sub
<<, >> shift
<<<, >>> arithmetic shift
<, <=, >, >= comparison
==, != equal, not equal
&, ~& AND, NAND
^, ~^ XOR, XNOR
|, ~| OR, NOR
Lowest ?: ternary operator

Slide derived from slides by Harris & Harris from their book 9
 Adder Examples
module fulladder(input logic a, b, cin,
output logic s, cout);
logic p, g; // internal nodes

assign p = a ^ b;
assign g = a & b;

assign s = p ^ cin;
assign cout = g | (p & cin);
endmodule s

g s

cin

cout
a
b
un1_cout cout
p
Slide derived from slides by Harris & Harris from their book 10
 Adder Examples
/* hierarchical 4-bit adder */
module h4ba(input logic [3:0] A, B,
input logic carry_in,
output logic [3:0] sum,
output logic carry_out);

logic carry_out_0, carry_out_1, carry_out_2; // internal signals

fulladder fa0 (A[0], B[0], carry_in, sum[0], carry_out_0);

fulladder fa1 (A[1], B[1], carry_out_0, sum[1], carry_out_1);
fulladder fa2 (A[2], B[2], carry_out_1, sum[2], carry_out_2);
fulladder fa3 (A[3], B[3], carry_out_2, sum[3], carry_out);

endmodule each of these is an instantiation

of “full_adder”

11
 Adder Examples
module add4(input logic [3:0] A, B,
output logic [3:0] sum);
assign sum = A + B;
endmodule Verilog compilers will replace arithmetic
operators with default logic implementations
(e.g. ripple carry adder)

this expands into logic for a

ripple carry adder

12
 Numbers
Format: N'Bvalue
N = number of bits, B = base
N'B is optional but recommended (default is decimal)
Number # Bits Base Decimal Stored
Equivalent
3'b101 3 binary 5 101
'b11 unsized binary 3 00…0011
8'b11 8 binary 3 00000011
8'b1010_1011 8 binary 171 10101011
3'd6 3 decimal 6 110
6'o42 6 octal 34 100010
8'hAB 8 hexadecimal 171 10101011
42 unsized decimal 42 00…0101010

Slide derived from slides by Harris & Harris from their book 13
 Bit Manipulations: Example 1
assign y = {a[2:1], {3{b[0]}}, a[0], 6'b100_010};

// if y is a 12-bit signal, the above statement produces:

// y = a[2] a[1] b[0] b[0] b[0] a[0] 1 0 0 0 1 0

// underscores (_) are used for formatting only to make

// it easier to read. SystemVerilog ignores them.

Slide derived from slides by Harris & Harris from their book 14
 Bit Manipulations: Example 2
module mux2_8(input logic [7:0] d0, d1,
input logic s,
output logic [7:0] y);

mux2 lsbmux(d0[3:0], d1[3:0], s, y[3:0]);

mux2 msbmux(d0[7:4], d1[7:4], s, y[7:4]);
endmodule

mux2
s s
[7:0] [3:0] [3:0] [7:0]
d0[7:0] d0[3:0] y[3:0] y[7:0]
[7:0] [3:0]
d1[7:0] d1[3:0]

lsbmux

mux2
s
[7:4] [7:4]
d0[3:0] y[3:0]
[7:4]
d1[3:0]

msbmux

Slide derived from slides by Harris & Harris from their book 15