Semiconductor

Memories
Lecture 1: May 10, 2006
EE Summer Camp
Abhinav Agarwal
Outline
 Concept/need of memory
 Parameters
 Types/classification
 Basic features
 Basic Cell circuits
 Peripheral circuitry
Concept
 Data storage essential for processing
 Binary storage
 Switches Write

'0'
Read
'1'

 How do you implement this in Hardware?

Requirements
 Easy reading
 Easy Writing
 High density
 Speed, more speed and still more speed
Memory Chip Configuration
Row Address
M
N bits 2 Cells

Memory Cell Array

Complete Address
N+M Bits

Row Dec
Cell
WL N
2 Cells
I/O Interface

DL

Din
din
I/O Control
Dout dout

Column Dec.
Control
Signals
Column Address
M Bits
Semiconductor Memory Classification

Non-Volatile
Read-Write Memory Read-Write Read-Only Memory
Memory

Random Non-Random EPROM Mask-Programmed

Access Access
E2PROM Programmable (PROM)

SRAM FIFO FLASH

DRAM LIFO
Shift Register
CAM

© Digital Integrated Circuits2nd Memories

RAM
 Random write and read operation for any cell
 Volatile data
 Most of computer memory
 DRAM
 Low Cost
 High Density
 Medium Speed
 SRAM
 High Speed
 Ease of use
 Medium Cost
ROM
 Non-volatile Data
 Method of Data Writing
 Mask ROM
 Data written during chip fabrication
 PROM
 Fuse ROM: Non-rewritable
 EPROM: Erase data by UV rays
 EEPROM: Erase and write through electrical means
 Speed 2-3 times slower than RAM
 Upper limit on write operations
 Flash Memory – High density, Low Cost
Basic Cells
 DRAM  SRAM

VDD

WL
WL
WL

DL
DL
DL
 Static CAM Memory Cell
Bit Bit Bit Bit
Word Bit Bit
M8 M9
M4 M5
CAM ••• CAM
M6 M7

Word
••• ••• Word S
int
S
CAM ••• CAM M3 M2
Match
M1

Wired-NOR Match Line

© Digital Integrated Circuits2nd Memories

 CAM in Cache Memory

CAM SRAM
ARRAY ARRAY

Hit Logic
Address Decoder
Input Drivers Sense Amps / Input Drivers

Address Tag Hit R/W Data

© Digital Integrated Circuits2nd Memories

ROM
 Fuse ROM  EEPROM

WL WL

Floating Gate

DL DL
 MOS NAND ROM
V DD
Pull-up devices

BL [0] BL [1] BL [2] BL [3]

WL [0]

WL [1]

WL [2]

WL [3]

All word lines high by default with exception of selected row

© Digital Integrated Circuits2nd Memories

 Non-Volatile Memories
The Floating-gate transistor (FAMOS)

Floating gate Gate

D
Source Drain

tox G

tox
S
n+ p n+_
Substrate

Device cross-section Schematic symbol

© Digital Integrated Circuits2nd Memories

 Floating-Gate Transistor Programming

20 V 0V 5V

10 V 5V 20 V - 5V 0V - 2.5 V 5V

S D S D S D

Avalanche injection Removing programming Programming results in

voltage leaves charge trapped higher V T .

© Digital Integrated Circuits2nd Memories

 A “Programmable-Threshold” Transistor

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 Periphery

 Decoders
 Sense Amplifiers
 Input/Output Buffers
 Control / Timing Circuitry

© Digital Integrated Circuits2nd Memories

 Row Decoders
Collection of 2M complex logic gates
Organized in regular and dense fashion

(N)AND Decoder

NOR Decoder

© Digital Integrated Circuits2nd Memories

 Hierarchical Decoders
Multi-stage implementation improves performance
•••

WL 1

WL 0

A 0A 1 A 0A 1 A 0A 1 A 0A 1 A 2A 3 A 2A 3 A 2A 3 A 2A 3

•••
NAND decoder using
2-input pre-decoders
A1 A0 A0 A1 A3 A2 A2 A3

© Digital Integrated Circuits2nd Memories

Sense Amplifiers
make D V as small
C  DV as possible
tp = ----------------
Iav

large small

Idea: Use Sense Amplifer

small
transition s.a.

input output

© Digital Integrated Circuits2nd Memories

 Sense Amp Operation

V BL V(1)

V PRE
D V(1)

V(0)
Sense amp activated t
Word line activated

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 Differential Sense Amplifier
V DD

M3 M4
y Out

bit M1 M2 bit

SE M5

Directly applicable to
SRAMs

© Digital Integrated Circuits2nd Memories

Reliability and Yield

© Digital Integrated Circuits2nd Memories

References
 Digital Integrated Circuits, 2nd Edition, Jan Rabaey,
Anantha Chandrakasan, Borivoje Nikolic
Chapter 12 http://bwrc.eecs.berkeley.edu/IcBook/slides.htm

 Sedra & Smith, Microelectronic Circuits, 4th Edition,

Chapter 13
 Section 13.9, 13.10, 13.11, 13.12

 VLSI Memory Chip Design, Kiyoo Itoh