Vivekananda Samantra CP15 05 01-Embedded Systems

EMBEDDED SYSTEMS
Vivekananda Samantra CP15 05 01- Embedded Systems

Contents:
Introduction
Block Diagram and Pin Description of the 8051
Registers
Some Simple Instructions
Structure of Assembly language and Running
an 8051 program
Memory mapping in 8051
8051 Flag bits and the PSW register
Addressing Modes
16-bit, BCD and Signed Arithmetic in 8051
Stack in the 8051
LOOP and JUMP Instructions
CALL Instructions
I/O Port Programming

Introduction
General-purpose microprocessor
• CPU for Computers
• No RAM, ROM, I/O on CPU chip itself
• Example ： Intel’s x86, Motorola’s 680x0
Many chips on mother’s board

Data Bus
CPU
General-
Serial
Purpose RAM ROM I/O Timer COM
Micro- Port
Port
processor
Address Bus
General-Purpose Microprocessor System

Microcontroller :
• A smaller computer
• On-chip RAM, ROM, I/O ports...
• Example ： Motorola’s 6811, Intel’s 8051, Zilog’s Z8 and PIC 16X
CPU RAM ROM

A single chip
Serial
I/O Timer COM
Port
Port
Microcontroller

Microprocessor vs. Microcontroller
Microprocessor Microcontroller
• CPU is stand-alone, RAM, • CPU, RAM, ROM, I/O and
ROM, I/O, timer are separate timer are all on a single chip
• designer can decide on the • fix amount of on-chip ROM,
amount of ROM, RAM and RAM, I/O ports
I/O ports. • for applications in which cost,
• expansive power and space are critical
• versatility • single-purpose
• general-purpose

Embedded System
• Embedded system means the processor is embedded into that

application.
• An embedded product uses a microprocessor or microcontroller to
do one task only.
• In an embedded system, there is only one application software that
is typically burned into ROM.
• Example ： printer, keyboard, video game player

Three criteria in Choosing a Microcontroller
1. meeting the computing needs of the task efficiently and cost

effectively
• speed, the amount of ROM and RAM, the number of I/O ports
and timers, size, packaging, power consumption
• easy to upgrade
• cost per unit
2. availability of software development tools
• assemblers, debuggers, C compilers, emulator, simulator,
technical support
3. wide availability and reliable sources of the microcontrollers.

Block Diagram
External interrupts
On-chip Timer/Counter
Interrupt ROM for

On-chip Timer 1 Counter
Control program
RAM Timer 0 Inputs
code
CPU
Bus Serial
4 I/O Ports
OSC Control Port
P0 P1 P2 P3 TxD RxD
Address/Data

Comparison of the 8051 Family Members
Feature 8051 8052 8031

ROM (program space in bytes) 4K 8K 0K
RAM (bytes) 128 256 128
Timers 2 3 2
I/O pins 32 32 32
Serial port 1 1 1
Interrupt sources 6 8 6

Pin Description of the 8051
P1.0 1 40 Vcc
P1.1 2 39 P0.0(AD0
P1.2 3 38 P
) 0.1(AD1)
P1.3
P1.4
4
5
8051 37
36
P0.2(AD2
P
) 0.3(AD3)
P1.5 6 (8031) 35 P0.4(AD4)
P1.6 7 34 P0.5(AD5)
P1.7 8 33 P0.6(AD6)
RST 9 32 P0.7(AD7)
(RXD)P3.0 10 31 EA/VPP
(TXD)P3.1 11 30 ALE/PROG
(INT0)P3.2 12 29 PSEN
(INT1)P3.3 13 28 P2.7(A15)
(T0)P3.4 14 27 P2.6(A14
(T1)P3.5 15 26 )P2.5(A13
(WR)P3.6 16 25 P
) 2.4(A12
(RD)P3.7 17 24 )P2.3(A11
XTAL2 18 23 P ) 2.2(A10)
XTAL1 19 22 P2.1(A9)
GND 20 21 P2.0(A8)

Pins of I/O Port
• The 8051 has four I/O ports

– Port 0 （ pins 32-39 ）： P0 （ P0.0 ～ P0.7 ）
– Port 1 （ pins 1-8 ）： P1 （ P1.0 ～ P1.7 ）
– Port 2 （ pins 21-28 ）： P2 （ P2.0 ～ P2.7 ）
– Port 3 （ pins 10-17 ）： P3 （ P3.0 ～ P3.7 ）
– Each port has 8 pins.
• Named P0.X （ X=0,1,...,7 ） , P1.X, P2.X, P3.X
• Ex ： P0.0 is the bit 0 （ LSB ） of P0
• Ex ： P0.7 is the bit 7 （ MSB ） of P0
• These 8 bits form a byte.
• Each port can be used as input or output (bi-direction).

Pins of 8051 （ 1/4 ）
• Vcc （ pin 40 ）：
– Vcc provides supply voltage to the chip.
– The voltage source is +5V.
• GND （ pin 20 ）： ground
• XTAL1 and XTAL2 （ pins 19,18 ）：
– These 2 pins provide external clock.
– Way 1 ： using a quartz crystal oscillator
– Way 2 ： using a TTL oscillator
– Example 4-1 shows the relationship between XTAL and the
machine cycle.

Example :
Find the machine cycle for

(a) XTAL = 11.0592 MHz
(b) XTAL = 16 MHz.
Solution:
(a) 11.0592 MHz / 12 = 921.6 kHz;

machine cycle = 1 / 921.6 kHz = 1.085 s
(b) 16 MHz / 12 = 1.333 MHz;
machine cycle = 1 / 1.333 MHz = 0.75 s

Example :
Find the machine cycle for

(a) XTAL = 11.0592 MHz
(b) XTAL = 16 MHz.
Solution:
(a) 11.0592 MHz / 12 = 921.6 kHz;

machine cycle = 1 / 921.6 kHz = 1.085 s
(b) 16 MHz / 12 = 1.333 MHz;
machine cycle = 1 / 1.333 MHz = 0.75 s
Vivekananda Samantra CP15 05 01- Embedded Systems 

Figure 4-2 (a). XTAL Connection to 8051
• Using a quartz crystal oscillator

• We can observe the frequency on the XTAL2 pin.
C2
XTAL2
30pF
C1
XTAL1
30pF
GND

Pins of 8051 （ 2/4 ）
• RST （ pin 9 ）： reset

– It is an input pin and is active high （ normally low ） .
• The high pulse must be high at least 2 machine cycles.
– It is a power-on reset.
• Upon applying a high pulse to RST, the microcontroller will
reset and all values in registers will be lost.
• Reset values of some 8051 registers
• Way 1 ： Power-on reset circuit
– Way 2 ： Power-on reset with debounce

Pins of 8051 （ 3/4 ）
• /EA （ pin 31 ）： external access enable

– There is no on-chip ROM in 8031 and 8032 .
– The /EA pin is connected to GND to indicate the code is stored
externally.
– /PSEN ＆ ALE are used for external ROM.
– For 8051, /EA pin is connected to Vcc.
– “/” means active low.
• /PSEN （ pin 29 ）： program store enable
– This is an output pin and is connected to the OE pin of the ROM.

Pins of 8051 （ 4/4 ）
• ALE （ pin 30 ）： address latch enable

– It is an output pin and is active high.
– 8051 port 0 provides both address and data.
– The ALE pin is used for de-multiplexing the address and data by
connecting to the G pin of the 74LS373 latch.
• I/O port pins
– The four ports P0, P1, P2, and P3.
– Each port uses 8 pins.
– All I/O pins are bi-directional.

Registers
A
R0
DPTR DPH DPL
R1
R2 PC PC
R3
R4 Some 8051 16-bit Register
R5
R6
R7
Some 8-bitt Registers of

the 8051

Memory mapping in 8051
• ROM memory map in 8051 family
4k 8k 32k
0000H 0000H 0000H
0FFFH
DS5000-32
1FFFH
8751
AT89C51
8752
AT89C52 7FFFH
from Atmel Corporation

from Dallas Semiconductor

• RAM memory space allocation in the 8051
7FH
Scratch pad RAM
30H
2FH
Bit-Addressable RAM
20H
1FH Register Bank 3
18H
17H
Register Bank 2
10H
0FH Register Bank 1 )Stack(
08H
07H
Register Bank 0
00H

RAM memory space allocation in the 8051
• Total of 128 bytes of RAM

inside the 8051 are assigned addresses 00H to 7FH
(a) Total of 32 bytes from locations 00H to 1FH
are set aside for register bank and the stack.
(b) Total of 16 bytes from locations 20H to 2FH
are set aside for bit addressable read/write memory.
(c) Total of 80 bytes from locations 30H to 7FH
are used for read and write storage, called “Scratch pad”
area used for storing data.

8051 Flag bits and the PSW register
• PSW Register
CY AC F0 RS1 RS0 OV -- P
Carry flag PSW.7 CY

Auxiliary carry flag PSW.6 AC
Available to the user for general purpose PSW.5 F0
Register Bank selector bit 1 PSW.4RS1
Register Bank selector bit 0 PSW.3RS0
Overflow flag PSW.2 OV
User define bit PSW.1 --
Parity flag Set/Reset odd/even parity PSW.0 P
RS1 RS0 Register Bank Address
0 0 0 00H-07H
0 1 1 08H-0FH
1 0 2 10H-17H
1 1 3 18H-1FH

Instructions that Affect Flag Bits:
Note: X can be 0 or 1

Structure of Assembly language and
Running an 8051 program
EDITOR
PROGRAM
Myfile.asm
ASSEMBLER
PROGRAM
Myfile.lst
Other obj file
Myfile.obj
LINKER
PROGRAM
Myfile.abs
OH
PROGRAM
Myfile.hex

Addressing Modes
• Immediate
• Register
• Direct
• Register Indirect
• Indexed

Immediate Addressing Mode
MOV A,#65H
MOV A,#’A’
MOV R6,#65H
MOV DPTR,#2343H
MOV P1,#65H
Example :
Num EQU 30
…
MOV R0,Num
MOV DPTR,#data1
…
ORG 100H
data1: db “IRAN”

Register Addressing Mode
MOV Rn, A ;n=0,..,7
ADD A, Rn
MOV DPL, R6
MOV DPTR, A
MOV Rn, Rn

Direct Addressing Mode
Although the entire of 128 bytes of RAM can be accessed
using direct addressing mode, it is most often used to access
RAM loc. 00 – 7FH.
MOV R0, 40H

MOV 56H, A
MOV A, 4 ; ≡ MOV A, R4
MOV 6, 2 ; copy R2 to R6
; MOV R6,R2 is invalid !
SFR register and their address
MOV 0E0H, #66H ; ≡ MOV A,#66H

MOV 0F0H, R2 ; ≡ MOV B, R2
MOV 80H,A ; ≡ MOV P0,A
Register Indirect Addressing Mode
• In this mode, register is used as a pointer to the data.
MOV A,@Rp ; move content of RAM loc.Where address is held by Ri into A

( i=0 or 1 )
MOV @R1,B
In other word, the content of register R0 or R1 is sources or target in MOV, ADD and SUBB
insructions.
Example:
Write a program to copy a block of 10 bytes from RAM location starting at 37h to RAM
location starting at 59h.
Solution:
MOV R0,37h ; source pointer
MOV R1,59h ; dest pointer
MOV R2,10 ; counter
L1: MOV A,@R0
MOV @R1,A
INC R0
INC R1
DJNZ R2,L1

Indexed Addressing Mode And On-Chip
ROM Access
• This mode is widely used in accessing data elements
of look-up table entries located in the program (code)
space ROM at the 8051
MOVC A,@A+DPTR
A= content of address A +DPTR from ROM
Note:
Because the data elements are stored in the program
(code ) space ROM of the 8051, it uses the instruction
MOVC instead of MOV. The “C” means code.
8051 instruction set
• MOV – copy the data from data memory
• MOVC – copy the data from code memory
• MOVX - copy the data from external memory

• MOV A,#data(8bit) – load accumulator with 8-bit data
eg: MOV A,#16h
A 16h
• MOV A,10h – the data from RAM location 10 will be
loaded to accumulator.
12
11
10 34
0F
0E A 34h

• MOV Rn,# data
Eg: MOV R4,#56h
R4 56h
• MOV 03h, # 45h
03h 45h (03 0r R3 is address)
• MOV A,Rn
Eg: MOV A,R3 – load Accumulator with the content of
R3
• MOV Rn,A
Rn A

• MOV addr(8),addr(8)
• To represent data starting with alphabets from A

to F, should be added 0 as prefix
Eg : MOV 00h,# 0AEh
MOV addr(8), A
Addr A
• MOV Rn,Rn is invalid

MOV A, @Rn – The content of memory
location whose address is stored in the register
Rp will be moved to the accumulator.
• MOV addr(8),@Rp
• MOV @Rp, #data
• MOV @Rp, A
• MOV @Rp,addr(8)

DATA POINTER
• The Data Pointer (DPTR) is the 8051s only user-
accessable 16-bit (2-byte) register. The
Accumulator, "R" registers, and "B" register are all
1-byte values.
• DPTR, as the name suggests, is used to point to
data. It is used by a number of commands which
allow the 8051 to access external memory. When
the 8051 accesses external memory it will access
external memory at the address indicated by DPTR.
• While DPTR is most often used to point to data in
external memory, many programmers often take
advantage of the fact that its the only true 16-bit
register available. It is often used to store 2-byte
values which have nothing to do with memory
locations.
MOVX
• Function: Move Data To/From External Memory (XRAM)
• Syntax: MOVX operand1,operand2
• Instructions
• MOVX @DPTR,A
• MOVX @Rp, A
• MOVX A,@DPTR
• MOVX A, @Rp
• Description: MOVX moves a byte to or from External

Memory into or from the Accumulator.
• If operand1 is @DPTR, the Accumulator is moved to the

16-bit External Memory address indicated by DPTR. This
instruction uses both P0 (port 0) and P2 (port 2) to output
the 16-bit address and data.
MOVX
• If operand2 is DPTR then the byte is moved
from External Memory into the Accumulator.
• If operand1 is @R0 or @R1, the Accumulator is
moved to the 8-bit External Memory address
indicated by the specified Register. This
instruction uses only P0 (port 0) to output the 8-
bit address and data.
• P2 (port 2) is not affected. If operand2 is @R0 or
@R1 then the byte is moved from External
Memory into the Accumulator.

MOVC
• Operation: MOVC
• Function: Move Code Byte to Accumulator
• Syntax: MOVC A, @A+register
• Instructions :
MOVC A,@A+DPTR
MOVC A,@A+PC
• Description: MOVC moves a byte from Code
Memory into the Accumulator. The Code Memory
address from which the byte will be moved is
calculated by summing the value of the
Accumulator with either DPTR or the Program
Counter (PC).
• In the case of the Program Counter, PC is first
incremented by 1 before being summed with the
Accumulator.
ARITHMETIC INSTRUCTIONS
• All addition is done with the ‘A’ register as the
destination of the result
• ADD A,#data(8) – A+data(8) A
• ADD A, Rn(n=0 to 7) – add A and the content of

Rn, result is in A
A+addr(8) A
• ADD A,add(8) - add A and the content of
address, result is in A
A+addr(8) A
• ADD A, @Rp (Rp is R0 or R1) – add the contents
of address in Rp ; put result in A

 ADDC – add with carry
• ADDC A,#data(8)
A + data(8)+ CY A
• ADDC A,Rn
A + Rn+CY A
• ADDC A,add(8)
A + addr(8)+CY A
• ADDC A,@Rp – add the content of A, the

content of indirect address in Rp,and the C flag;
put result in A
 SUBTRACTION
• Subtraction can be done by taking the
two’s complement of the number to be
subtracted, the subtrahend and adding it
to the other number.
• The 8051 has commands to perform the
direct subtraction of two unsigned and
signed numbers.
• Like addition Register A is the destination
address for the subtraction.
• Subtraction always subtract the carry flag
(borrow) as part of the operation
Subtraction
• SUBB A,#data(8)
A - data(8)- CY A
• Subtract immediate data(8) and the C Flag from
A and the result will be in A.
• SUBB A, add(8)
A – add(8) - CY A
• SUBB A, Rn
A- Rn- CY A
SUBB A, @Rp: Subtract the contents of the

address in Rp and the C Flag from A and result
is stored in A
Unsigned subtraction
• In the above instruction C Flag is always
subtracted from A along with the source byte.
• It must be set to 0, if programmer does not want
the carry Flag to be included in the subtraction.
• In a multibyte subtraction the carry flag has to be
cleared for first byte and then included for the
subsequent higher byte operations.
• The result will be in the true form, with no borrow
if the source number is smaller than A.
• The result will be in Two’s complement form,
with borrow if the source is larger than A.
• All bits are considered as the magnitude.
Multiplication and Division
• The 8051 has the capability to perform
8-bit integer multiplication and division using A and B
registers.
• Multiplication: Multiplication use registers A and B as
both source and destination addresses.
 MUL AB – multiply A by B; put the lower byte of
the product in A, and the higher order byte in B
• The unsigned number in register A is multiplied with the
unsigned number in register B and the result will be
stored in A, if the product is less than FF h.
• If the product is greater than FF h, the OV Flag will be
Set. The higher order bytes will be stored in register B
and lower order bytes in register A.
• The carry flag is always cleared to 0.
Example
• MOV A, #7B H ;A=7Bh
MOV 0F0h,#02h ;B=02h
MUL AB ;A=F6h and B=00h,OV=0
MOV B, #0FEh ;B= FEh
MUL AB ;A=14h, B=F4h,OV Flag=1

Division
• Division operation use registers A and B
as both the source and destination
addresses for the operation.
 DIV AB – Divide A by B; the integer
part of quotient in register A and the
integer part of the remainder in B.
• The OV flag is cleared to 0 unless B holds
00h before the DIV. Then the overflow flag
is set to 1 to show division by 0. This
division is undefined.
• The Samantra
Vivekananda carry flagCP15
is05always reset.
01- Embedded Systems
• Example
MOV A,#0FFh - A = FFh

MOV 0F0h,#2Ch - B = 2Ch
DIV AB - A = 05h and B = 23h
DIV AB - A = ? and B = ?; OV = 1

Decimal arithmetic
• Most of the real world application which
involves interacting with the human
beings, which insists the numbering to be
done in decimal number system.
• Four bits are required to represent the
decimal 0-9 (0000h-1001h)
 DA A – Adjust the sum of two packed
BCD numbers found in A register;
result in A
• The DA A will work with the instruction
ADDC or ADD.
INCREMENT
• Operation: INC
 No flags are affected(C,AC,OV)
• Function: Increment Register
• Instructions
• INC A
• INC Rn
• INC @Rp
• INC addr
• INC DPTR
• Description: INC increments the value of
register or content of address by 1.
• In the case of "INC DPTR", the value two-byte
unsigned integer value of DPTR is incremented.
Decrement
• Operation:DEC
• Instructions
• DEC A
• DEC Rn
• DEC @Rp
• DEC addr(8)
• Description: DEC decrements the value
of register or the content of address by 1.

Clear
• Operation:CLR
• Instructions
• CLR addr(8) – Clear the content of address
specified
• CLR C – Clear carry flag
• CLR A – Clear the content of accumulator
• Description: CLR clears (sets to 0) all the bit(s)
of the indicated register. If the register is a bit
(including the carry bit), only the specified bit is
affected. Clearing the Accumulator sets the
Accumulator’s value to 0.
Logical Instruction
• Operation: CPL
• Function: Complement
• Syntax: CPL operand
• Instructions
• CPL A - complement each bit of A
• CPL C - complement Carry
• CPL addr(8) - complement each bit of the

content of address specified.

AND operation
• Operation: ANL
• Function: Bitwise AND
• Instructions
• ANL addr(8), A –AND each bit of A with same bit
of direct RAM address and store the result in addr(8)
• ANL A,addr(8) -AND each bit of A with same bit
of direct RAM address and store the result in A
• ANL addr(8), #data
• ANL A, #data
• ANL A, Rn
• ANL A, @Rp
• ANL A,R0
• ANL C, bit addr
XOR
• Operation: XRL
• Function: Bitwise Exclusive OR
• Instructions
• XRL addr(8), A
• XRL addr(8), #data
• XRL A, #data
• XRL A, addr(8)
• XRL A, @Rp
• Description: XRL does a bitwise "EXCLUSIVE

OR" operation between operand1 and operand2,
leaving the resulting value in operand1. The
value of operand2 is not affected.
OR Operation
• Operation: ORL
• Function: Bitwise OR
• Instructions
• ORL addr(8), A
• ORL addr(8), #data
• ORL A, #data
• ORL A, addr(8)
• ORL A,@R0
• ORL C, bit
• Description: ORL does a bitwise "OR" operation

between operand1 and operand2, leaving the resulting
value in operand1. The value of operand2 is not affected.
RR – RL – RRC – RLC A
EXAMPLE:
RR A
RR:
RRC: C
RL:
RLC: C
ROTATE LEFT
• Operation: RL
• Function: Rotate Accumulator Left
• Syntax: RL A
• Description: Shifts the bits of the Accumulator to the left.
The left-most bit -bit 7 of the Accumulator is loaded into
bit0.
• Operation: RLC
• Function: Rotate Accumulator Left Through Carry
• Syntax: RLC A
• Description: Shifts the bits of the Accumulator to the left.
The left-most bit (bit 7) of the Accumulator is loaded into
the Carry Flag, and the original Carry Flag is loaded into
bit 0 of the Accumulator. This function can be used to
quickly multiply a byte by 2.
ROTATE RIGHT
• Operation: RR
• Function: Rotate Accumulator Right
• Syntax: RR A
• Description: Shifts the bits of the Accumulator to the
right. The right-most bit -bit 0 of the Accumulator is
loaded into bit7.
• Operation: RRC
• Function: Rotate Accumulator Right Through Carry
• Syntax: RRC A
• Description: Shifts the bits of the Accumulator to the
right. The right-most bit (bit 0) of the Accumulator is
loaded into the Carry Flag, and the original Carry Flag is
loaded into bit 7. This function can be used to quickly
divide a byte by 2.
LOOP and JUMP Instructions
Conditional Jumps :
JZ Jump if A=0
JNZ Jump if A/=0
DJNZ Decrement and jump if A/=0

CJNE A, byte Jump if A/=byte
CJNE reg, #data Jump if byte/=#data
JC Jump if CY=1
JNC Jump if CY=0
JB Jump if bit=1
JNB Jump if bit=0
JBC Jump if bit=1 and clear bit

LJMP(long jump)
LJMP is an unconditional jump. It is a 3-byte instruction. It
allows a jump to any memory location from 0000 to FFFFH.
AJMP(absolute jump)
In this 2-byte instruction, It allows a jump to any memory
location within the 2k block of program memory.
SJMP(short jump)
In this 2-byte instruction. The relative address range of 00-
FFH is divided into forward and backward jumps, that is ,
within -128 to +127 bytes of memory relative to the address of
the current PC.

JMP
• Operation: JMP
• Function: Jump to Data Pointer +
Accumulator
• Syntax: JMP @A+DPTR
• Description: JMP jumps unconditionally
to the address represented by the sum of
the value of DPTR and the value of the
Accumulator.

CJNE
• Operation: CJNE
• Function: Compare and Jump If Not Equal
• Syntax: CJNE operand1,operand2,reladdr
• CJNE A, #data ,relative-address
– Compare the content of the accumulator and the data and
branch to the relative address if not equal
• CJNE A, addr(8),relative-address
• CJNE @Rp, #data, relative-address
• Description: CJNE compares the value of operand1 and

operand2 and branches to the indicated relative address
if operand1 and operand2 are not equal. If the two
operands are equal program flow continues with the
instruction following the CJNE instruction.
• The Carry bit (C) is set if operand1 is less than
operand2, otherwise it is cleared.
JNC
• Operation: JNC
• Function: Jump if Carry Not Set
• Syntax: JNC reladdr
• Description: JNC branches to the
address indicated by reladdr if the carry bit
is not set. If the carry bit is set program
execution continues with the instruction
following the JNC instruction.
JC
• Operation: JC
• Function:Jump if Carry Set
• Syntax:JC reladdr
• Description: JC will branch to the address
indicated by reladdr if the Carry Bit is set.
If the Carry Bit is not set program
following the JC instruction.
JNZ
• Operation: JNZ
• Function: Jump if Accumulator Not Zero
• Syntax:JNZ reladdr
• Description: JNZ will branch to the
address indicated by reladdr if the
Accumulator contains any value except 0.
If the value of the Accumulator is zero
program execution continues with the
instruction following the JNZ instruction.
JZ
• Operation: JZ
• Function:Jump if Accumulator Zero
• Syntax:JZ reladdr
• Description: JZ branches to the address
indicated by reladdr if the Accumulator
contains the value 0. If the value of the
Accumulator is non-zero program
following the JZ instruction.
JNB
• Operation: JNB
• Function: Jump if Bit Not Set
• Syntax: JNB bit addr, reladdr
• Description: JNB will branch to the
address indicated by relative address if the
indicated bit is not set. If the bit is set
program execution continues with the
instruction following the JNB instruction.
JB
• Operation: JB
• Function:Jump if Bit Set
• Syntax:JB bit addr, reladdr
• Description: JB branches to the address
indicated by relative address if the bit
indicated by bit addr is set. If the bit is not
set program execution continues with the
instruction following the JB instruction.
JBC
• Operation: JBC
• Function: Jump if Bit Set and Clear Bit
• Syntax: JB bit addr, reladdr
• Description: JBC will branch to the address
indicated by reladdr if the bit indicated by bit
addr is set. Before branching to reladdr the
instruction will clear the indicated bit. If the bit is
not set program execution continues with the
instruction following the JBC instruction.

SETB
• Operation: SETB
• Function: Set Bit
• Syntax: SETB bit addr
• Description: Sets the specified bit.

SWAP
• Operation: SWAP
• Function: Swap Accumulator Nibbles
• Syntax: SWAP A
• Description:
• SWAP swaps bits 0-3 of the Accumulator
with bits 4-7 of the Accumulator.
• This instruction is identical to executing
"RR A" or "RL A" four times.
PUSH
• Operation: PUSH
• Function: Push Value Onto Stack
• PUSH addr(8);
• Description: PUSH "pushes" the value of
the specified addr(8) onto the stack. PUSH
first increments the value of the Stack
Pointer by 1, then takes the value stored in
internal RAM addr and stores it in Internal
RAM at the location pointed to by the
incremented Stack Pointer.
POP
• Operation: POP
• Function: Pop Value From Stack
• Syntax: POP
• POP addr(8)
• Description: POP "pops" the last value placed
on the stack into the internal RAM address
specified. In other words, POP will load addr(8)
with the value of the Internal RAM address
pointed to by the current Stack Pointer. The
stack pointer is then decremented by 1.

CALL Instructions
Another control transfer instruction is the CALL instruction,
which is used to call a subroutine.
LCALL(long call)
This 3-byte instruction can be used to call subroutines
located anywhere within the 64K byte address space
of the 8051.
ACALL (absolute call)
ACALL is 2-byte instruction. The target address of the
subroutine must be within 2K byte range.

RETURN
• Operation: RET
• Function: Return From Subroutine
• Syntax: RET
• Description: RET is used to return from a
subroutine previously called by LCALL or
ACALL.
• Program execution continues at the address
that is calculated by popping the topmost 2
bytes off the stack.
• The most-significant-byte is popped off the stack
first, followed by the least-significant-byte.
XCH
• Function: Exchange Bytes
• Syntax: XCH A, Rn
• XCH A, @Rp
• XCH A, addr
• Description: Exchanges the value of the
Accumulator with the value contained in
register.

XCHD
• Function: Exchange Digit
• Syntax: XCHD A,@Rp
• XCHD A,@R0
• XCHD A,@R1
• Description: Exchanges bits 0-3 of the
Accumulator with bits 0-3 of the Internal RAM
address pointed to indirectly by R0 or R1.
• Bits 4-7 of each register are unaffected.
• Eg: RAM location 40H = 97H
MOV A,#12H
MOV R1,#40H
XCHD A,@R1
After execution ACP15
Vivekananda Samantra
= 17H and RAM location 40H =92H
05 01- Embedded Systems
• Operation: NOP
• Function: None, waste time
• Syntax: No Operation
• Description: NOP, as it’s name suggests,
causes No Operation to take place for one
machine cycle.
• NOP is generally used only for timing
purposes. Absolutely no flags or registers
are affected.

THANK YOU..

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EMBEDDED SYSTEMS

Vivekananda Samantra CP15 05 01- Embedded Systems

Vivekananda Samantra CP15 05 01- Embedded Systems

Many chips on mother’s board

General-Purpose Microprocessor System

Vivekananda Samantra CP15 05 01- Embedded Systems

CPU RAM ROM

Vivekananda Samantra CP15 05 01- Embedded Systems

Vivekananda Samantra CP15 05 01- Embedded Systems

• Embedded system means the processor is embedded into that

Vivekananda Samantra CP15 05 01- Embedded Systems

1. meeting the computing needs of the task efficiently and cost

Vivekananda Samantra CP15 05 01- Embedded Systems

Interrupt ROM for

Vivekananda Samantra CP15 05 01- Embedded Systems

Feature 8051 8052 8031

Vivekananda Samantra CP15 05 01- Embedded Systems

Vivekananda Samantra CP15 05 01- Embedded Systems

• The 8051 has four I/O ports

Vivekananda Samantra CP15 05 01- Embedded Systems

Find the machine cycle for

(a) 11.0592 MHz / 12 = 921.6 kHz;

Vivekananda Samantra CP15 05 01- Embedded Systems

Find the machine cycle for

(a) 11.0592 MHz / 12 = 921.6 kHz;

Vivekananda Samantra CP15 05 01- Embedded Systems 

• Using a quartz crystal oscillator

Vivekananda Samantra CP15 05 01- Embedded Systems

• RST （ pin 9 ）： reset

Vivekananda Samantra CP15 05 01- Embedded Systems

• /EA （ pin 31 ）： external access enable

Vivekananda Samantra CP15 05 01- Embedded Systems

• ALE （ pin 30 ）： address latch enable

Vivekananda Samantra CP15 05 01- Embedded Systems

R4 Some 8051 16-bit Register

Some 8-bitt Registers of

Vivekananda Samantra CP15 05 01- Embedded Systems

• ROM memory map in 8051 family

from Atmel Corporation

Vivekananda Samantra CP15 05 01- Embedded Systems

Scratch pad RAM

Vivekananda Samantra CP15 05 01- Embedded Systems

• Total of 128 bytes of RAM

Vivekananda Samantra CP15 05 01- Embedded Systems

Carry flag PSW.7 CY

RS1 RS0 Register Bank Address

Vivekananda Samantra CP15 05 01- Embedded Systems

Vivekananda Samantra CP15 05 01- Embedded Systems

Vivekananda Samantra CP15 05 01- Embedded Systems

Vivekananda Samantra CP15 05 01- Embedded Systems

Vivekananda Samantra CP15 05 01- Embedded Systems

Vivekananda Samantra CP15 05 01- Embedded Systems

MOV R0, 40H

SFR register and their address

MOV 0E0H, #66H ; ≡ MOV A,#66H

MOV A,@Rp ; move content of RAM loc.Where address is held by Ri into A

Vivekananda Samantra CP15 05 01- Embedded Systems

• MOVC – copy the data from code memory

• MOVX - copy the data from external memory