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Optimized BIST Based Radix-4 Booth Multiplier Using FPGA New

This document describes a project to design an optimized built-in self-test (BIST) for a Radix-4 Booth multiplier using an FPGA. A test pattern generator with a low register-to-bit ratio is used to generate random test patterns. A Radix-4 Booth algorithm and gate-level adders are used in the multiplier design. Simulation results show the proposed BIST design has lower power and area than existing methods while maintaining high speed. The BIST can be used for applications like avionics and medical devices that require self-testing.

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kranthi
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83 views18 pages

Optimized BIST Based Radix-4 Booth Multiplier Using FPGA New

This document describes a project to design an optimized built-in self-test (BIST) for a Radix-4 Booth multiplier using an FPGA. A test pattern generator with a low register-to-bit ratio is used to generate random test patterns. A Radix-4 Booth algorithm and gate-level adders are used in the multiplier design. Simulation results show the proposed BIST design has lower power and area than existing methods while maintaining high speed. The BIST can be used for applications like avionics and medical devices that require self-testing.

Uploaded by

kranthi
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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OPTIMIZED BIST BASED RADIX-4 BOOTH MULTIPLIER USING FPGA

OPTIMIZED BIST BASED RADIX-


4 BOOTH MULTIPLIER USING
FPGA

INTERNAL GUIDE, M.KRANTHI KIRAN


M.RENUKA,ASSIST.PROF,VLSI M.TECH(VLSI 1ST SHIFT)
ECE,DEPT. ROLL.NO.15911D5712

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OPTIMIZED BIST BASED RADIX-4 BOOTH MULTIPLIER USING FPGA

AIM OF PROJECT

 Increasing application of integrated circuit in day-to-day


useful electronic gadgets.

 High speed and Low power.

 Fastest increasing applications.

 Multiplier are very important logic operational.

 Important feature of hardware designs in self-testing


ability.
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OPTIMIZED BIST BASED RADIX-4 BOOTH MULTIPLIER USING FPGA

INTRODUCTION

 (BIST) built –in-self-testing ability.

 Logic operation DATA Input.

 When it is operated in Self-Test mode.

 This test sequence is operated by Logic

 The comparator output indicates logic high.


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OPTIMIZED BIST BASED RADIX-4 BOOTH MULTIPLIER USING FPGA

BIST BLOCK DIAGRAM DESIGN

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OPTIMIZED BIST BASED RADIX-4 BOOTH MULTIPLIER USING FPGA

PROPOSED METHOD
 For the BIST implementation, a TPG with random output
value is required.

 For TPG realization, a low-power modified design of


(LFSR) is used in this design implementation.

 A 3-register is used for the generation of a 4-bit random


number(register-to-bit ration of 3:4).

 The presented TPG generates a repetitive sequence of four


random numbers of 4-bit in sequence

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OPTIMIZED BIST BASED RADIX-4 BOOTH MULTIPLIER USING FPGA

TEST PATTERN GENERATOR USED IN


PROPOSEDDESIGN
 Three flip-flop with linear feed-back are used.
 The output of the last flip-flop is XOR-ed with the control
input Enable to initiate the random number generation.

 The outputs of the first two flip-flops are XOR-ed to


generate the fourth output bit of the TPG.

 This circuit generates a 4-bit random value using only 3-


registers

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OPTIMIZED BIST BASED RADIX-4 BOOTH MULTIPLIER USING FPGA

RANDOM SEQUENCE GENERATION


BY TPG

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OPTIMIZED BIST BASED RADIX-4 BOOTH MULTIPLIER USING FPGA

MULTIPLIER

 The BIST based approach for the implementation of a


multiplier using a configurable hardware.

 A 4-bit low power multiplier design is used as a test logic


design

 A gate level combination is used to generate a half-adder


and a full-adder design.

 These adder design block are used in combination to

generate the multiplier using the adder terms.


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OPTIMIZED BIST BASED RADIX-4 BOOTH MULTIPLIER USING FPGA

BOOTH’S RECODING RADIX 4

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OPTIMIZED BIST BASED RADIX-4 BOOTH MULTIPLIER USING FPGA

ADVANTAGES

 At-speed of testing for delay and stuck-at faults.

 Drastic ATE cost reduction.

 In-field testing capability.

 Repeatable test procedures.

 Faster diagnosis during system test.

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OPTIMIZED BIST BASED RADIX-4 BOOTH MULTIPLIER USING FPGA

COMPARASSION TABLE
EXITING METHOD PROPOSED
METHOD

Power=0.318(w) Power=0.158(w)

Area= no.slice:90 Area=no.slice:83

Speed=179ns Speed=163ns

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OPTIMIZED BIST BASED RADIX-4 BOOTH MULTIPLIER USING FPGA

APPLICATION
 Avionics

 Medical device

 Automotive electronics

 Safety-critical device.

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OPTIMIZED BIST BASED RADIX-4 BOOTH MULTIPLIER USING FPGA

RADIX4 WAVEFORM

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OPTIMIZED BIST BASED RADIX-4 BOOTH MULTIPLIER USING FPGA

BIST SIMULATE BHAVIORAL MODEL

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OPTIMIZED BIST BASED RADIX-4 BOOTH MULTIPLIER USING FPGA

RTL SCHEMATIC SYMBOL

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OPTIMIZED BIST BASED RADIX-4 BOOTH MULTIPLIER USING FPGA

CONCLUSION

 The built-in-self-test application is a 4-bit multiplier and


the test pattern generator is also designed for generating a
random 4-bit number.

 The test pattern generator is a modified design that has a


low register-to-bit ratio,

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OPTIMIZED BIST BASED RADIX-4 BOOTH MULTIPLIER USING FPGA

 The number of out bits in the generated sequence is

more than the number of registers in Thus, with respect

to the previously proposed designs of TPG

It involves less number of registers and hence a low-

power design realization is obtained using this TPG

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OPTIMIZED BIST BASED RADIX-4 BOOTH MULTIPLIER USING FPGA

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