Unit-I

Advanced Processors
ARM7,ARM9 & ARM11 Processors
 Contents
• Introduction to ARM processors and it’s versions
• ARM7,ARM9 &ARM11 features
• Advantages and suitability in embedded application
• Registers, CPSR,SPSR
• ARM and RISC design philosophy
• ARM7 data flow model
• Programmers model
• Modes of operations
• Introduction to Tiva TM4C123G series overview
• Programming model
• Tivaware Library
 Contents
• Introduction to ARM processors and it’s versions
• ARM7,ARM9 &ARM11 features
• Advantages and suitability in embedded application
• Registers, CPSR,SPSR
• ARM and RISC design philosophy
• ARM7 data flow model
• Programmers model
• Modes of operations
• Introduction to Tiva TM4C123G series overview
• Programming model
• Tivaware Library
 ARM and RISC design philosophy
Key Points to discuss….
1. Processor performance measures
(Speed, throughput and Peripheral Interaction)
2. Pipeline advancements
3. Core Vs. Controller /Processor
4. Why RISC architecture ?
5. Architecture Evolution is towards applications
 Quick Review of CISC
• Fast context switching (smaller process environment to
handle)
• Powerful assembly language programming facility
• Reduced requirements on compiler design (machine
language forms a layer of abstraction)
• Flexibility of processor operation via microcode
modifications (writable control store or ROM change)
• Powerful and fast floating-point operations (highly
sophisticated instructions)
• Reduced memory requirements (programs require less
memory)
• Improved cache performance (due to smaller program size)
• Reduced bus traffic (highly sophisticated instructions require
less memory access to do the same job)
 RISC Features

• Large register files

• Emphasis on register-oriented operations
• Instructions that primarily execute in a single cycle
• Simple LOAD/STORE instructions for memory access
• Limited addressing modes
• Fixed-length instructions that do not span word
boundaries
• Hard-coded logic (as opposed to microcode driven)
• Pipelined instruction cycle (typically uniform delay
pipelines)
 RISC Advantages…..
• Fast instruction execution (simple compact instructions;
surveys show most often used)
• Simple control unit (less instructions and addressing
modes to be handled)
• Fast decode (limited instructions and addressing modes;
fixed size instructions)
• Highly efficient pipelined parallel execution (fixed-length
and simple instructions)
• Faster processor design, development, and test (simpler
design)
• Fast instruction execution (simple compact instructions;
surveys show most often used)
 RISC Advantages…..
• Improved optimizing compiler support (simple machine
language generally preferred)
• Reduced pipeline branching penalties (due to delayed
branch technique used in many RISCs)
• Improved subroutine parameter passing speed (register
windows)
• …………………………………………………………..
Comparison at a glance
 RISC Design Philosophy
• Instruction

• Pipeline

• Registers

• Load and store

Early days Today's trend
 ARM Design Philosophy
advantages /Suitability towards Embedded System
Hardware Aspect (Technology Perspective)
• Low Power
• High code density
• Reduced die area
• Adoption of standard bus architecture
• Hardware debug technology
 ARM Design Philosophy
advantages /Suitability towards Embedded System
Software Aspect (Developers’ Perspective)
• Variable cycle executions for certain Instructions
• Inline barrel shifter
• Thumb Instruction
• Conditional Execution
• Enhanced Instructions
Typical Embedded Hardware
 Typical ARM Feature..
• Large Uniform Register file

• Load /store architecture

• Simple addressing modes

• Uniform and simple Instruction fields

 NonRISC ARM features
• Control over both the Arithmetic Logic Unit(ALU) and
shifter in every data-processing instruction to
maximize the use of an ALU and a shifter.
• auto-increment and auto-decrement addressing
modes to optimize program loops
• Load and Store Multiple instructions to maximize
data throughput
• conditional execution of all instructions to maximize
execution throughput.
• Orthogonal instruction Set
ARM Versions
 Development of the ARM Architecture
Improved
5TE Jazelle
Halfword and
signed
4 ARM/Thumb
Interworking Java bytecode 5TEJ
1 halfword /
CLZ execution
byte support
System mode SA-110 Saturated maths ARM9EJ-S ARM926EJ-S
2 DSP multiply-
SA-1110 ARM7EJ-S ARM1026EJ-S
accumulate
instructions
3 ARM1020E SIMD Instructions
Thumb
instruction 4T Multi-processing
6
set XScale
Early ARM V6 Memory
architectures architecture (VMSA)
ARM7TDMI ARM9TDMI ARM9E-S
Unaligned data support
ARM720T ARM940T ARM966E-S ARM1136EJ-S
(MPU)
 ARM Processor Nomenclature
• ARM {x}{y}{z}-{T}{D}{M}{I}{E}{J}{F}{S}
• X: family,
• y: Memory Mangmt/Protection,
• Z : Cache
• I : Embedded ICE macrocell
• F: Vector floating point unit
• S: Synthesizable version ( Core is provided as
source code and used by EDA tools)
 ARM9 Features
• Von Neuman  Harvard Architecture (modified Harvard)
• 3 stage pipeline 5 stage pipeline
• Enhanced clock speed (x2)
• Faster load and store
• Exposing pipeline interlock (support of compiler optimization)
• Memory management and protection
• ARM Jazelle technology which enables the direct
execution of 8-bit Java byte code in hardware
 ARM11 Features
• SIMD instructions (which can double MPEG-4 and audio digital signal
processing algorithm speed)
• Cache is physically addressed (solving many cache aliasing problems
and reducing context switch overhead)
• Unaligned and mixed-endian data access is supported
• Reduced heat production and lower overheating risk
• Redesigned pipeline, supporting faster clock speeds (target up
to 1 GHz)
– Longer: 8 (vs 5) stages
– Out-of-order completion for some operations (e.g. stores)
– Dynamic branch prediction/folding (like XScale)
– Cache misses don't block execution of non-dependent instructions
– Load/store parallelism
– ALU parallelism
• 64-bit data paths
• Accelerated IRQ response
• Vector floating point unit
ARM Core (Data flow model)
 ARM Operating modes

--- User : unprivileged mode under which most tasks run

– FIQ : entered when a high priority (fast) interrupt is raised

– IRQ : entered when a low priority (normal) interrupt is raised

– Supervisor : entered on reset and when a Software Interrupt

instruction is executed

– Abort : used to handle memory access violations

– Undef : used to handle undefined instructions

– System : privileged mode using the same registers as user mode

ARM Processor Modes
Programmers Model

Spsr is
Available in
All modes
Except user.
 The ARM Register Set

Current Visible Registers

r0
Abort
Undef
FIQ
IRQ
User Mode
SVCMode
Mode
Mode
r1
r2
r3 Banked out Registers
r4
r5
r6 User FIQ IRQ SVC Undef Abort
r7
r8 r8 r8
r9 r9 r9
r10 r10 r10
r11 r11 r11
r12 r12 r12
r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp)
r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr)
r15 (pc)

cpsr
spsr spsr spsr spsr spsr spsr
 Register Organization Summary
User FIQ IRQ SVC Undef Abort
r0
r1
User
r2 mode
r3 r0-r7,
r4 r15, User User User User
and mode mode mode mode Thumb state
r5
cpsr r0-r12, r0-r12, r0-r12, r0-r12, Low registers
r6
r15, r15, r15, r15,
r7 and and and and
r8 r8 cpsr cpsr cpsr cpsr
r9 r9
r10 r10 Thumb state
r11 r11 High registers
r12 r12
r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp)
r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr)
r15 (pc)

cpsr
spsr spsr spsr spsr spsr

Note: System mode uses the User mode register set

 The Registers
• ARM has 37 registers all of which are 32-bits long.
– 1 dedicated program counter
– 1 dedicated current program status register
– 5 dedicated saved program status registers
– 30 general purpose registers

• The current processor mode governs which of several banks is accessible.

Each mode can access
– a particular set of r0-r12 registers
– a particular r13 (the stack pointer, sp) and r14 (the link register, lr)
– the program counter, r15 (pc)
– the current program status register, cpsr

Privileged modes (except System) can also access

– a particular spsr (saved program status register)
 Program Status Registers
31 28 27 24 23 16 15 8 7 6 5 4 0

N Z C V Q J U n d e f i n e d I F T mode
f s x c
• Condition code flags • Interrupt Disable bits.
– N = Negative result from ALU – I = 1: Disables the IRQ.
– Z = Zero result from ALU – F = 1: Disables the FIQ.
– C = ALU operation Carried out
– V = ALU operation oVerflowed • T Bit
– Architecture xT only
• Sticky Overflow flag - Q flag – T = 0: Processor in ARM state
– Architecture 5TE/J only – T = 1: Processor in Thumb state

– Indicates if saturation has

occurred • Mode bits
• J bit – Specify the processor mode
– Architecture 5TEJ only
– J = 1: Processor in Jazelle state
 Program Counter (r15)
• When the processor is executing in ARM state:
– All instructions are 32 bits wide
– All instructions must be word aligned
– Therefore the pc value is stored in bits [31:2] with bits [1:0] undefined
(as instruction cannot be halfword or byte aligned).

• When the processor is executing in Thumb state:

– All instructions are 16 bits wide
– All instructions must be halfword aligned
– Therefore the pc value is stored in bits [31:1] with bit [0] undefined (as
instruction cannot be byte aligned).

• When the processor is executing in Jazelle state:

– All instructions are 8 bits wide
– Processor performs a word access to read 4 instructions at once
 Exception Handling
• When an exception occurs, the ARM:
– Copies CPSR into SPSR_<mode>
– Sets appropriate CPSR bits
• Change to ARM state
• Change to exception mode
• Disable interrupts (if appropriate) 0x1C FIQ
– Stores the return address in LR_<mode> 0x18 IRQ
– Sets PC to vector address 0x14 (Reserved)
0x10 Data Abort
• To return, exception handler needs to:
0x0C Prefetch Abort
– Restore CPSR from SPSR_<mode>
0x08 Software Interrupt
– Restore PC from LR_<mode> 0x04 Undefined Instruction
This can only be done in ARM state. 0x00 Reset
Vector Table
Vector table can be at
0xFFFF0000 on ARM720T
and on ARM9/10 family devices
Tiva™ TM4C123G Series Overview
 Reference material
Sr.No Topic Reference

1. ARM and RISC Design Philosophy 1.Andrew Sloss, Dominic Symes, Chris Wright, ―ARM
System Developer‘s Guide – Designing and Optimizing
System Software‖, ELSEVIER
2.Advanced Microprocessors . By Tabak
2. Introduction to ARM processors and its versions 1.Andrew Sloss, Dominic Symes, Chris Wright, ―ARM
System Developer‘s Guide – Designing and Optimizing
System Software‖, ELSEVIER
3 ARM7, ARM9 & ARM11 features 1.Andrew Sloss, Dominic Symes, Chris Wright, ―ARM
System Developer‘s Guide – Designing and Optimizing
System Software‖, ELSEVIER
2.web pages
4. advantages & suitability in embedded application Andrew Sloss, Dominic Symes, Chris Wright, ―ARM
System Developer‘s Guide – Designing and Optimizing
System Software‖, ELSEVIER
5. ARM7 data flow model, programmers model, 1.ARM architecture reference manual :www.arm.com
modes of operations 2. Andrew Sloss, Dominic Symes, Chris Wright, ―ARM
System Developer‘s Guide – Designing and Optimizing
System Software‖, ELSEVIER

7. . Introduction to Tiva TM4C123G Series Overview White paper