ECE 424 – Introduction to VLSI

Design
Emre Yengel

Department of Electrical and

Communication Engineering

Fall 2014
Introduction
• Sequential circuit
o Output depends not just on present inputs (as in combinational
circuit), but on past sequence of inputs
• Stores bits, also known as having “state”
o Simple example: a circuit that counts up in binary

Inputs Outputs
COMBINATIONAL
LOGIC

Current State
Next state
Registers
Q D

CLK
• A sequential circuit consists of a feedback path, and employs some memory
elements.
Introduction
• Flight attendant call button Call Blue light

▫ Press call: light turns on button

Cancel
Bit
Storage

 Stays on after button button

released 1. Call button pressed – light turns on

▫ Press cancel: light turns off Call Blue light

button
▫ Logic gate circuit to Cancel
Bit
Storage
a

implement this? button

2. Call button released – light stays on

Call Q
a
Cancel Call Blue light
button Bit
Doesn’t work. Q=1 when Call=1, but Cancel Storage
button
doesn’t stay 1 when Call returns to 0
3. Cancel button pressed – light turns off
Need some form of “feedback” in the circuit
Memory Elements
• There are two types of sequential circuits:
o synchronous: outputs change only at specific time
o asynchronous: outputs change at any time

• Multivibrator: a class of sequential circuits. They can be:

• bistable (2 stable states)
• monostable or one-shot (1 stable state)
• astable (no stable state)

Bistable logic devices: latches and registers

• a latch is level sensitive

• a register is edge-triggered

• Many books call edge-triggered elements flip-flops.

Standard Memory Elements

 Memory element with clock.

Memory Q
command element stored value

clock

 Clock is usually a square wave.

Positive pulses

Positive edges Negative edges

Timing Definitions

t Register
tsu thold D Q

D DATA CLK
STABLE t
tc 2 q

Q DATA
STABLE t

setup time (tsu)

hold time (thold)
propagation delay (tc-q)
Latches vs Registers

 Latch  Register
stores data when stores data when
clock is low or high clock rises

D Q D Q

Clk Clk

Clk Clk

D D

Q Q
Latches
Static Latches and Registers:
Bistability Principle

V o1 Vi2

V i1 V o2

A
When the gain of the inverter in the
V i 2 = V o1
transient region is larger than 1, only A
and B are stable operation points, and C is C
a metastable operation point.
B
V i 1 = V o2
Bistability Principle

Gain should be larger than 1 in the transition region

SR Latches
SR latch
• Does the circuit to the right, with cross-coupled S (set)

NOR gates, do what we want?

R (reset)
S=0 S=0 S=1 S=0
t t t t Recall…
1 1 0 0 0
0 0 1 1 1
0

1
1 1 0 0 0
0 Q 0 Q 1 1 X
Q Q

R=1 R=0 R=0 R=0

1
S
0
R1
0 a

t 1
0
1
Q
0
SR Latches
 Characteristics table for active-high input S-R latch (also
known as NOR gate latch):
S R Q Q'
0 0 NC NC No change. Latch
remained in present state. S Q
1 0 1 0 Latch SET.
0 1 0 1 Latch RESET. R Q'
1 1 0 0 Invalid condition.

 Characteristics table for active-low input S'-R' latch (also

known as NAND gate latch):
S' R' Q Q'
1 1 NC NC No change. Latch
remained in present state. S Q
0 1 1 0 Latch SET.
1 0 0 1 Latch RESET. R Q'
0 0 1 1 Invalid condition.
SR Latches
• Problem
▫ If S=1 and R=1 simultaneously, we don’t know what value Q will
take
1
S
0
1
R
0
1
t
0
1
Q
0

1
Q may oscillate. Then, because one path will be t
0
slightly longer than the other, Q will eventually 1
settle to 1 or 0 – but we don’t know which. Q
0
SR Latches

• Problem not just one of a user pressing two buttons at

same time
• Can also occur even if SR inputs come from a circuit
that supposedly never sets S=1 and R=1 at same time
▫ But does, due to different delays of different paths
Arbitrary
circuit S SR latch
X

Y R

The longer path from X to R than to S causes SR=11 for

short time – could be long enough to cause oscillation
Level Sensitive SR Latches
• Add enable input “C” as shown Level-sensitive SR latch
S
▫ Only let S and R change when C=0 S1
 Enure circuit in front of SR never sets SR=11,
except briefly due to path delays
C
▫ Change C to 1 only after sufficient time for S
and R to be stable Q
▫ When C becomes 1, the stable S and R value R
passes through the two AND gates to the SR R1
latch’s S1 R1 inputs.
S
Q’
Level-sensitive SR latch Though SR=11 briefly... C
1 Q
S S R
X S1 0
1 Level-sensitive
R0
SR latch symbol
C 1 a
Clk C
0
Q 1
S1
R 0
R1
Y 1
R1 0

...S1R1 never = 11
Clock Signals of a Latch

• How do we know when it’s safe to set C=1?

▫ Most common solution –make C pulse up/down
 C=0: Safe to change X, Y Level-sensitive SR latch
 C=1: Must not change X, Y S
X S1
 We’ll see how to ensure that later
▫ Clock signal -- Pulsing signal used to enable
latches Clk
C

 Because it ticks like a clock Q

▫ Sequential circuit whose storage components all R
R1
use clock signals: synchronous circuit Y

 Most common type

 Asynchronous circuits – important topic, but left for
advanced course
Clocks

• Clock period: time interval between

pulses Freq Period
▫ Above signal: period = 20 ns 100 GHz 0.01 ns
• Clock cycle: one such time interval 10 GHz 0.1 ns
▫ Above signal shows 3.5 clock cycles 1 GHz 1 ns
• Clock frequency: 1/period 100 MHz 10 ns
10 MHz 100 ns
▫ Above signal: frequency = 1 / 20 ns = 50
MHz
 1 Hz = 1/s
Level Sensitive D Latch

• SR latch requires careful design to D latch

D
ensure SR=11 never occurs S

• D latch relieves designer of that C

burden
Q
▫ Inserted inverter ensures R R
always opposite of S
1
D
0 D Q’

1 C Q
C
0
D latch symbol
1
S
0
1
R
0
1
Q
0
Problem with Level-Sensitive D Latch
• D latch still has problem (as does SR latch)
▫ When C=1, through how many latches will a signal
travel?
▫ Depends on for how long C=1
 Clk_A -- signal may travel through multiple latches
 Clk_B -- signal may travel through fewer latches
▫ Hard to pick C that is just the right length
 Can we design bit storage that only stores a value on the
rising edge of a clock signal?
Y D1 Q1 D2 Q2 D3 Q3 D4 Q4 Clk

C1 C2 C3 C4

Clk

Clk_A Clk_B
Flip-Flop
• Flip-flop: Bit storage that stores on clock edge, not level rising edges
• One design -- master-servant Clk
▫ Two latches, output of first goes to input of second, master
latch has inverted clock signal
Note:
▫ So master loaded when C=0, then servant when C=1 Hundreds of
▫ When C changes from 0 to 1, master disabled, servant loaded different flip-
flop designs
with value that was at D just before C changed -- i.e., value at exist
D during rising edge of C

D flip-flop
D latch D latch
D Q’
Dm Qm Ds Qs’
Q
Cm Cs Qs
master servant

Clk
Edge-Triggered Flip-Flops
 S-R, D and J-K edge-triggered flip-flops. Note
the “>” symbol at the clock input.

S Q D Q J Q
C C C
R Q' Q' K Q'

Positive edge-triggered flip-flops

S Q D Q J Q
C C C
R Q' Q' K Q'

Negative edge-triggered flip-flops

S-R Flip-Flop

 S-R flip-flop: on the triggering edge of the clock

pulse,
S=HIGH (and R=LOW) a SET state
R=HIGH (and S=LOW) a RESET state
both inputs LOW a no change
both inputs HIGH a invalid
 Characteristic table of positive edge-triggered S-R
flip-flop:
S R CLK Q(t+1) Comments
0 0 X Q(t) No change
0 1  0 Reset
1 0  1 Set
1 1  ? Invalid

X = irrelevant (“don’t care”)

 = clock transition LOW to HIGH
S-R Flip-Flop
 It comprises 3 parts: S
Q
 a basic NAND latch Pulse
CLK transition
 a pulse-steering circuit detector
Q'
 a pulse transition detector (or edge R
detector) circuit
 The pulse transition detector The pulse transition detector.
detects a rising (or falling) edge
and produces a very short-
duration spike.
CLK' CLK'
CLK CLK* CLK CLK*

CLK CLK

CLK' CLK'

CLK* CLK*

Positive-going transition Negative-going transition

(rising edge) (falling edge)
D Flip-Flop

D Q’ D Q’ Internal design: Just

The triangle invert servant clock
means clock Q Q rather than master
input, edge
triggered
Symbol for rising-edge Symbol for falling-edge
triggered D flip-flop triggered D flip-flop

rising edges falling edges

Clk Clk
D Flip-Flop
• Solves problem of not knowing through how many latches a signal
travels when C=1
▫ In figure below, signal travels through exactly one flip-flop, for Clk_A or
Clk_B
▫ Why? Because on rising edge of Clk, all four flip-flops are loaded
simultaneously -- then all four no longer pay attention to their input, until
the next rising edge. Doesn’t matter how long Clk is 1.

Y D1 Q1 D2 Q2 D3 Q3 D4 Q4
Two latches inside
each flip-flop

Clk

Clk_A Clk_B
D-Latch vs. D-Flip-Flop

• Latch is level-sensitive: Stores D when C=1

• Flip-flop is edge triggered: Stores D when C changes
from 0 to 1
▫ Saying “level-sensitive latch,” or “edge-triggered flip-
flop,” is redundant
▫ Two types of flip-flops -- rising or falling edge triggered.
• Comparing behavior of latch and flip-flop:
Flight-Attendant Call Button Using D Flip-Flop

• D flip-flop will store bit Call

Flight Blue
• Inputs are Call, Cancel, and present value button
attendant light
Cancel call-button
of D flip-flop, Q button system

• Truth table shown below

Preserve value: if Circuit derived from truth table,

Q=0, make D=0; if using combinational logic design
Q=1, make D=1 process

Cancel -- make Call Call

but ton D Q’
Blue
D=0 light
Cancel Cancel
but ton
Clk Q
Call -- make D=1 Q

Let’s give priority

to Call -- make
D=1
D Flip-Flop
 Application: Parallel data transfer.
To transfer logic-circuit outputs X, Y, Z to flip-
flops Q1, Q2 and Q3 for storage.
D Q Q1 = X*

CLK
Q'
X
Combinational Y D Q Q2 = Y*
logic circuit
Z CLK
Q'

D Q Q3 = Z*
Transfer CLK
Q'

* After occurrence of negative-going transition

J-K Flip-Flop
 J-K flip-flop: Q and Q' are fed back to the pulse-steering
NAND gates.
 No invalid state.
 Include a toggle state.
 J=HIGH (and K=LOW) a SET state
 K=HIGH (and J=LOW) a RESET state
 both inputs LOW a no change
 both inputs HIGH a toggle

J
Q
Pulse
CLK transition
detector
Q'
K

J-K flip-flop.
J-K Flip-Flop
 J-K flip-flop.
J
Q
Pulse
CLK transition
detector
Q'
K

 Characteristic table. Q J K Q(t+1)

0 0 0 0
J K CLK Q(t+1) Comments 0 0 1 0
0 0  Q(t) No change 0 1 0 1
0 1  0 Reset 0 1 1 1
1 0  1 Set 1 0 0 1
1 1  Q(t)' Toggle 1 0 1 0
1 1 0 1
Q(t+1) = J.Q' + K'.Q 1 1 1 0
T Flip-Flop
 T flip-flop: single-input version of the J-K flip
flop, formed by tying both inputs together.
T
Q T J
Pulse Q
CLK transition CLK C
detector
Q' K Q'

 Characteristic
T CLK
table.
Q(t+1) Comments Q T Q(t+1)
0  Q(t) No change 0 0 0
1  Q(t)' Toggle 0 1 1
1 0 1
1 1 0
Q(t+1) = T.Q' + T'.Q
Summary
SR latch Level-sensitive SR latch D latch D flip-flop
S (set) S D
S1 S D latch D latch
D Q’
DmQm Ds Qs’
C C Q
Cm Cs Qs
Q Q Q master servant
R
R1 R Clk
R (reset)

Feature: S=1 sets Feature: S and R only Feature: SR can’t be 11 if Feature: Only loads D value
Q to 1, R=1 resets have effect when C=1. D is stable before and present at rising clock edge, so
Q to 0. Problem: We can design outside while C=1, and will be 11 values can’t propagate to other
SR=11 yield circuit so SR=11 never for only a brief glitch even flip-flops during same clock
undefined Q. happens when C=1. if D changes while C=1. cycle. Tradeoff: uses more
Problem: avoiding SR=11 Problem: C=1 too long gates internally than D latch,
can be a burden. propagates new values and requires more external
through too many latches: gates than SR – but gate count
too short may not enable a is less of an issue today.
store.

• We considered increasingly better bit storage until

we arrived at the robust D flip-flop bit storage