TRENDS AND CHALLENGES IN VLSI

BY:

Bhanuteja Labishetty
 OVERVIEW

 Introduction

 Technology Scaling

 Challenges in DSM digital design

 Design challenges of technology Scaling

 Design challenges of low power

 Active power management

 Leakage power management

 Challenges in VLSI circuit reliability

 Future direction in microprocessors systems

 Conclusion
 In the last three decades the world of computers and

especially that of microprocessors has been advanced at

exponential rates in both productivity and performance. The

integrated circuit industry has followed a steady path of

constantly shrinking devices geometries and increased

functionality that larger chips provide. The technology that

enabled this exponential growth is a combination of

advancements in process technology, microarchitecture,

architecture and design and development tools.

 Each new generation has approximately doubled logic circuit density
and increased performance by about 40% .

Moore’s law:

In 1965, Gordon Moore noted that the number of transistors on a chip

doubled every 18 to 24 months.

 He made a prediction that semiconductor technology would double its

effectiveness every 18 months

 Moore’s law continues to drive the scaling of CMOS technology. The

feature size of the transistor now has been shrunk well into Nano-scale
region.

 A large single VLSl chip can contain over one billion transistor.
 The ever-increasing level of integration has enabled higher
performance and richer feature sets on a single chip.

 As the geometry of the transistor is getting smaller and the

number of transistors on a single chip grows exponentially, the
power management for a state-of-the-art VLSI design has become
increasingly important.

 To maintain the performance trend of the vlsi system as the

technology scaling continues, many advanced design techniques,
especially in power management, have to be employed in order to
achieve a balanced design to meet platform and end-user needs.
INTRODUCTION
 During the past 40 years the semiconductor VLSI IC industry has
distinguished itself both by rapid pace of performance improvements
in its products, and by a steady path of constantly shrinking device
geometries and increasing chip size.

 The speed and integration density of IC’s have dramatically improved.

Exploitation of a billion transistor capacity of a single VLSI IC
requires new system paradigms and significant improvements to
design productivity.

 Structural complexity can be increased by having more productive

design methods and by putting more resources in design work.
 According to International Technology Roadmap for Semiconductor
(IRTS) projections, the number of transistors per chip and the local
clock frequencies for high-performance microprocessors will continue
to grow exponentially in the next 10 years too.
 The general trends, that we expect in the next ten years, according to
ITRS projections concerning:

 Increasing of transistor count for microprocessors and DRAM

memory elements.

 Shrinking of linewidths of IC’s.

 Growing chip die sizes and Increasing semiconductor fabrication

process complexity
Technology scaling:

 Linear dimension shrinks by

0.7𝑥
𝑇𝑒𝑐ℎ𝑛𝑜𝑙𝑜𝑔𝑦 𝑔𝑒𝑛𝑒𝑟𝑎𝑡𝑖𝑜𝑛

 Every generation can integrate 2x

more functions per chip

 But – How to design chips with more

and more functions?
– Design engineering population does
not double every two years…

 Hence, a need for more efficient

design methods
CHALLENGES IN DSM DIGITAL DESIGN

∝ (𝒎𝒊𝒏. 𝒇𝒆𝒂𝒕. 𝒔𝒊𝒛𝒆) ∝ 𝟏Τ(𝒎𝒊𝒏. 𝒇𝒆𝒂𝒕. 𝒔𝒊𝒛𝒆)

Microscopic Issue Macroscopic Issue

 Ultra high speed design  Time to market

 Interconnect  Millions of gates

 Noise , Crosstalk  High-Level Abstractions

 Reliability, Manufacturability  Reuse & IP: Portability

 Power Dissipation  Predictability

 Clock distribution  Etc…..

 Exponential growth rates have occurred for other aspects of computer
technology such as clock speed and processor performance.

 Shrinking linewidths not only enables more components to fit onto an

IC (typically 2x per linewidth generation) but also lower costs
(typically 30% per linewidth generation).
 Shrinking linewidths have slowed down the rate of growth in die size to
1.14x per year versus 1.38 to 1.58x per year for transistor counts, and
since the mid-nineties accelerating linewidth shrinks have halted and
even reversed the growth in die sizes.
 Shrinking linewidths isn’t free. Linewidth shrinks require process
modifications to deal with a variety of issues that come up from
shrinking the devices - leading to increasing complexity in the
processes being used

Design Challenges of Technology Scaling:

 Advances in optical lithography have allowed manufacturing of on -
chip structures with increasingly higher resolution.

 The area, power, and speed characteristics of transistors with a

planar structure, such as MOS devices, improve with the decrease
(i.e. scaling) in the lateral dimensions of the devices. Therefore, these
technologies are referred as scalable
Generally, scalable technology has three main goals:

 Reduce gate delay by 30%, resulting in an increase in Operating

frequency of about 43%

 Double transistor density and

 Reduce energy per transition by about 65%, saving 50% of power, at a

43% increase in frequency

 Scaling a technology reduces gate by 30% and the lateral and vertical
dimensions by 30%. Therefore, the area and fringing capacitance, and
consequently the total capacitance, decrease by 30% to 0.7 from nominal
value normalized to 1. Since the dimensions decrease by 30%, the die area
decrease by 50%, and capacitance per unit of area increases by 43%
DESIGN CHALLENGES OF LOW POWER
 The electronic devices at the heart of such products need to dissipate
low power, in order to conserve battery life and meet packaging
reliability constraints.
 Lowering power consumption is important not only for lengthening
battery life in portable systems, but also for improving reliability, and
reducing heat-removal cost in high-performance systems.
 Consequently, power consumption is a dramatic problem for all
integrated circuits designed today
 Following figure shows the relative impact on power consumption of
each phase of the design process. Essentially higher - level categories
have more effect on power reduction.
 Low power design in terms of algorithms, architectures, and circuits has
received significant attention and research input over the last decade.

Higher System level Design partitioning, Power down

Impact

Algorithm Complexity, concurrency, locality,

level Regularity, Data representation

Architecture Voltage Scaling, Parallelism,

level Instruction set, Signal correlation

Transistor sizing, Logical

optimization, Activity driven
Circuit level power down, Low swing logic,
Adiabatic Switching

Process device Threshold Reduction, Multi

level Threshold
ACTIVE POWER MANAGEMENT:
Reducing Switching Activities:
 For a high-frequency digital design, the clock power often represents a significant
portion of the overall switching power.

 The clock signals are driving a large number of sequential elements in a

synchronized system.

 The frequency scaling continues to drive up the overall use of the timing elements,
including latches and flip-flops.

 One of the most effective ways to reduce the switching power is through clock
gating.

 By dividing the chip into different clock domains and gating the clock signals
with block enable signals, it can greatly reduce the overall chip power.
Dynamic Voltage swing:
 To ensure a chip provide a high-level of performance while not getting
into reliability issues induced by on-die over-heating, an ability to
intelligently scale both voltage and frequency dynamically.

 The power and frequency scaling can be managed through either

operating system or can be triggered in flight by many on-die thermal
sensors that are positioned strategically across the die

 The on-die thermal sensor is critical in managing the “hot-spots”

where junction temperature could exceed reliability limit if now
controlled.
LEAKAGE POWER MANAGEMENT
Sleep transistor:
 As transistor geometry gets smaller, the leakage components, including
both sub threshold and gate leakage, have become more and more.

 The leakage power can potentially take up a significant portion of the

overall chip power.

 One of the most effective techniques in reducing the transistor leakage is

to introduce sleep transistor between normal circuit block and power
supply rails, either or both VCC and VSS.

 The sleep transistors can be shut off completely during idle state or
whenever the blocks are not being accessed.
 When the sleep transistors are turned off, the power supplies at VCC and
or VSS across the function block will be collapsing towards the middle.

 As a result, the voltage difference across the transistor gate as well as

source and drain is lowered, which reduces the leakage significantly.

Multiple Power Supplies:

 Since each functional block on a chip often requires different supply
voltage in order to achieve optimal power and performance trade off at
local level.

 One effective way to minimize the power consumption is to introduce

different power supplies locally.
 When certain circuit blocks are in idle state, a lower power supply can be
given to keep the leakage power at minimum.

 When the circuits are in active state, a higher power supply can be given
to provide optimum performance.

Frequency Scaling:

The figure shows that the

voltage level is decreasing
due to the scaling of the size
of the channel.
 The average number of gate delays in a clock period is decreasing
because both the new microarchitectures use shorter pipelines for static
gates, and because the advanced circuit techniques reduce the critical
path delays even further. This could be the main reason that the
frequency is doubled in every technology generation.
 The twofold frequency improvement for each technology generation is
primarily due to the following factors

 The reduced number of gates employed in a clock period, what

makes the design more pipelined.

 Advanced circuit design techniques that reduce the average gate

delay beyond 30% per generation.
CHALLENGES IN VLSI CIRCUIT RELIABILITY
 Shrinking geometries, lower power voltages, and higher frequencies
have a negative impact on reliability. Together, they increase the number
of occurrences of intermittent and transient faults.

 Faults experienced by semiconductor devices fall into three main

categories: permanent, intermittent, and transient.

Permanent Faults:
Permanent faults reflect irreversible physical changes. The
improvement of semiconductor design and manufacturing techniques has
significantly decreased the rate of occurrence of permanent faults.
 The Figure shows the evolution of permanent - fault rates for CMOS
microprocessors and static and dynamic memories over the past decade.

 The semiconductor industry is widely adopting copper interconnects. This

trend has a positive impact on permanent - faults rate of occurrence, as
copper provides a higher electro migration threshold than aluminium
does.
Intermittent Faults
Intermittent faults occur because of unstable or marginal hardware;
they can be activated by environmental changes, like higher or lower
temperature or voltage. Many times intermittent precede the occurrence of
permanent faults.

Transient faults

Transient faults occur because of temporary environmental

conditions. Several phenomena induce transient faults: neutron and alpha
particles; power supply and interconnect noise, electromagnetic
interference, and electrostatic discharge.
 Higher VLSI integration and lower supply voltages have contributed to
higher occurrence rates for particle - induced transients, also known as
soft errors.

 Following plot measured neutron - and alpha - induced soft errors rates
(SERs) for CMOS SRAMs as a function of memory capacity.
FAULT AVOIDANCE AND FAULT TOLERANCE

 Fault avoidance and fault tolerance are the main approaches used to
increase the reliability of VLSI circuits.

 Fault avoidance relies on improved materials, manufacturing processes,

and circuit design. For instance, lower - alpha emission interconnect
and packaging materials contribute to low SERs.

 Silicon on insulator is commonly used process solution for lower

circuit sensitivity to particle - induced transients
 Fault tolerance is implementable at the circuit or system level. It relies on
concurrent error detection, error recovery, error correction codes (CEDs), and
space or time redundancy.

 Intermittent and transient faults are expected to represent the main source of
errors experienced by VLSI circuits.

 Failure avoidance, based on design technologies and process technologies,

would not fully control intermittent and transient faults.

 Fault - tolerant solutions, presently employed in custom – designed systems,

will become widely used in off-the-shelf ICs tomorrow, i.e. in mainstream
commercial applications.
 The transient errors we will consider the influences of changes in the
supply voltage referred to as power supply noise. Power supply noise
adversely affects circuit operation through the following mechanisms:
a) signal uncertainty
b) on-chip clock jitter
c) noise margin degradation and
d) degradation of gate oxide reliability.

 For correct circuit operation the supply levels have to be maintained

within a certain range near the nominal voltage levels.

 This range is called the power noise margin.

 The primary objective in the design of the distribution system is to
supply sufficient current to each transistor on an integrated circuit
while ensuring that the power noise does not exceed the target noise
margins.

 As an illustration, the evolution of the average current of high-

performance Intel family of microprocessors is given in Figure.
FUTURE DIRECTIONS IN MICROPROCESSOR
SYSTEMS

 Deep-submicron technology allows billions of transistors on a single die,

potentially running at gigahertz frequencies.

 According to Semiconductor Industry Association projections, the

number of transistor per chip and the local clock frequencies for high
performance microprocessors will continue to grow exponentially in the
near future, as it is illustrated in Figure below.

 This ensures that future microprocessors will become even more

complex.
CONCLUSION
As technology scales, important new opportunities emerge for VLSI
ICs designers. Understanding technology trends and specific applications is
the main criterion for designing efficient and effective chips. There are
several difficult and exciting challenges facing the design of complex ICs.
To continue its phenomenal historical growth and continue to follow
Moore’s law, the semiconductor industry will require advances on all fronts
– from front-end process and lithography to design innovative high-
performance processor architectures, and SoC solutions. The roadmap’s goal
is to bring experts together in each of these fields to determine what those
challenges are, and potentially how to solve them.