8086 Interrupts and Interrupt

Applications

MICROPROCESSORS & MICROCONTROLLERS 1

 What is an interrupt?
• capability to suspend the execution of running
program and execution of another program to
fulfill specific requirement upon request

• after finishing the second program,

automatically return to the first program and
start execution from where it was left
 Interrupt overview
• Most microprocessors allow normal program execution
to be interrupted by some external signal or by a special
instruction in the program.
• In response to an interrupt, the microprocessor stops
executing its current program and calls a procedure
which “services” the interrupt.
• A special instruction --- IRET --- at the end of interrupt-
service procedure returns execution to the interrupted
main program.
 Interrupt Cycle Of 8086/8088
• Suppose an external device interrupts the CPU at the interrupt pin,
either NMI or INTR of the 8086, while the CPU is executing an
instruction of a program then 8086 performs following steps,
1. The CPU first completes the execution of the current instruction.
2. The IP is then incremented to point to the next instruction.
3. The CPU then acknowledges the requesting device on its INTA
bar pin immediately if it is a NMI, TRAP or Divide by zero
interrupt.
4. If it is an INT request, the CPU checks the IF flag.
5. If IF is set, the interrupt request is acknowledged using the INTA
bar pin. If IF is not set, the interrupt requests are ignored.
6. After an interrupt is acknowledged, CPU computes the vector
address from the type of interrupt that may be passed through the
interrupt structure of the CPU internally (in case of software
interrupt, NMI, TRAP and divide by zero interrupts) or externally,
i.e. from an interrupt controller in case of external interrupts.
7. The contents of IP and CS are next pushed to the stack.
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 Interrupt Cycle Of 8086/8088
6. The contents of IP and CS now point to the address of the next
instruction of the main program from which the execution is to be
continued after executing the ISR.
7. The PSW is also pushed to the stack.
8. The interrupt flag (IF) is cleared.
9. The TF is also cleared, after every response to the single step
interrupt.
10.The control is then transferred to the interrupt service routine for
serving the interrupting device.
11.The new address of ISR is found out from interrupt vector table.
12.The execution of ISR starts.
13.If further interrupts are to be responded to during the time the first
interrupt is being serviced, the IF should again be set to 1 by the
ISR of the first interrupt.
• Note that the responses to the NMI, TRAP and divide by zero
interrupt requests are independent of the IF flag.
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 Interrupt Cycle Of 8086/8088
• If the interrupt flag is not set, the subsequent interrupt
signals will not acknowledged by the processor, till the
current one is completed.
• The programmable interrupt controller is used for
managing such multiple interrupts based on their
priorities.
• At the end of ISR the last instruction should be IRET.
When the CPU executes IRET, the contents of flags, IP
and CS which were saved at the start by the CALL
instruction are now retrieved to the respective registers.
• The execution continues onwards from this address,
received by IP and CS.
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 Interrupt Cycle Of 8086/8088
• Every external and internal interrupt is assigned with a type
(N) that is either implicit (in case of NMI, TRAP and divide
by zero) or specified in the instruction INT N (in case of
internal interrupts.) in case of external interrupts, the type is
passed to the processor by an external hardware like
programmable interrupt controller.
• In the 0th segment of physical address space i.e. CS=0000,
Intel has reserved 1024 locations for storing the interrupt
vector table.
• The 8086 supports a total of 256 types of the interrupts i.e.
from 00 to FFH.
• Each interrupt requires 4 bytes, i.e. two bytes each for IP and
CS of its ISR.
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 Interrupt Cycle Of 8086/8088
• Thus a total of 1024 bytes are required for 256 interrupts types,
hence the interrupt vector table starts at location 0000: 0000 and ends
at 0000: 03FF H.

• The interrupt vector table contains the IP and CS of all the interrupt
types stored sequentially from address 0000: 0000 to 0000: 03FF H.
• The interrupt type N is multiplied by 4 and the hexadecimal
multiplication obtained gives the offset address in the 0th code
segment at which the IP and CS addresses of the interrupt service
routine (ISR) are stored.

• The execution automatically starts from the new CS: IP.

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 Interrupt Cycle Of 8086/8088

Interrupt Response Sequence

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 8086 Interrupt Response
1. Push FLAGS Interrupt Service
main
2. Clear IF Routine (ISR)
Program
3. Clear TF
4. Push CS PUSH registers
5. Push IP ...
6. Fetch ISR
...
address
...
....
POP IP
...
POP CS
....
POP FLAGS
POP registers
IRET
How does 8086 get to Interrupt
Service Routine?
– Simple. It loads its CS and IP registers with the
address of ISR.
– So, the next instruction to be executed is the
first instruction of ISR
How does 8086 get the address of
Interrupt Service Routine (ISR)?
–It goes to specified memory location to
fetch four consecutive bytes
• higher two bytes to be used as CS
• lower two bytes to be used as IP
How does 8086 get the address of
that specified memory location?
• In an 8086 system, the first 1Kbytes of memory, from
00000 to 003FF, is set aside as a Table for storing the
starting addresses of interrupt service routines.
– Since 4 bytes are required to store CS and IP
values for each ISR, the Table can hold the starting
addresses for up to 256 ISRs.
 8086 Interrupt Pointer Table
• The starting address of an ISR is often called
– the interrupt vector or
– the interrupt pointer.
• So the Table is referred to as
– interrupt-vector table or
– interrupt-pointer table.
 8086 Interrupt Pointer Table
• Next slide shows how the 256 interrupt vectors
are arranged in the table in memory
• Note that
– the IP value is put in as the low word of the vector
– CS as high word of the vector
• Each double word interrupt vector is identified
by a number from 0 to 255
• INTEL calls this number the TYPE of the
interrupt
 AVAILABLE 3FFH TYPE 255
FOR USER
...
(224) 080H TYPE 32
TYPE 31
RESERVED (27)
...
014H TYPE 5
TYPE 4
010H INTO OVERFLOW

TYPE 3
Predefined/ 00CH INT
Dedicated/Internal TYPE 2
Interrupts Pointers 008H NON-MASKABLE
(5) TYPE 1
004H SINGLE STEP
CS Base Address TYPE 0
IP Offset 000H DIVIDE ERROR
 How does 8086 get the address of a
particular ISR?
• In an 8086 system, each “interrupter” has an id#
• 8086 treat this id# as interruption type#
• after receiving INTR signal, 8086 sends an INTA signal
• after receiving INTA signal, interrupter releases it’s id#,
i.e., type# of the interruption.
• 8086 multiplies this id# or type# by 4 to produced the
desired address in the vector table
• 8086 reads 4 bytes of memory starting from this address to
get the starting address of ISR
• lower 2 byte is loaded in to IP
• higher 2 bytes to CS
 Non-Maskable Interrupt
• The processor 8086/88 has a non-maskable interrupt pin
(NMI), that has the highest priority among the external
interrupts.
• TRAP is an internal interrupt having the highest priority
among the interrupts except the Divide by zero (Type-0)
exception.
• The NMI pin should remain high for at least two clock
cycles and need not synchronized with the clock for being
sensed.
• When the NMI is activated, the current instruction being
executed is completed and then the NMI is served.
• In case of string type instructions, this interrupt will be
served only after the complete string has been
manipulated. 18
 Maskable Interrupt
• The processor 8086/88 also provides a pin INTR that has lower
priority as compared to NMI.
• Further the priorities within the INTR types are decided by the type
of the INTR signal that is to be passed to the processor via data bus
by some external device like the programmable interrupt controller.
• The INTR signal is level triggered and can be masked by resetting
the interrupt flag.
• It is internally synchronized with the transition of the clock. For the
INTR signal, to be responded to in the next instruction cycle, it
must go high in the last clock cycle of the current instruction or
before that.
• The INTR requests appearing after the last clock cycle of the
current instruction will be responded to after the execution of the
next instruction.
• The status of the pending interrupts is checked at the end of each
instruction cycle.
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 Maskable Interrupt
• If the IF is set, the processor is ready to respond to any
INTR interrupt if the IF is reset, the processor will not
serve any interrupt appearing at this pin.
• However, once the processor responds to an INTR signal,
the IF is automatically reset.
• If one wants the processor to further respond to any type
of INTR signal, the IF should again be set.
• The interrupt acknowledge sequence is as shown in
figure.
• Suppose the external signal interrupts the processor and
the pin LOCK bar goes low at the trailing edge of the first
ALE pulse that appears after the interrupt signal
preventing the use of bus for any other purpose.
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 Maskable Interrupt
• The pin LOCK bar remains low till the start of next
machine cycle.
• When trailing the trailing edge of the LOCK bar, the
INTA goes low and remains low for two clock states
before returning back to the high state.
• It remains high till the start of the next machine cycle
i.e. next trailing edge of ALE.
• Then INTA again goes low, remains low for the two
states before returning to the high state.
• The first trailing edge of ALE floats the bus AD0 - to -
AD7, while second trailing edge prepares the bus to
accept the type of interrupt.
• The type of interrupt remains on the bus for a period of
two cycles.
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 Maskable Interrupt
Interrupt acknowledge sequence of 8086

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Interrupt Programming

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 Interrupt Programming
• While programming for any type of interrupt, the programmer
must, either externally or through the program, set interrupt vector
table for that type preferably with the CS and IP addresses of the
interrupt service routine.
• The method of defining the interrupt service routine for software as
well as hardware is the same.
• To execute the above program,
– first assemble it using MASM.EXE, link it using LINK.EXE.
– Then execute the above program at a DOS prompt.
– After execution, you will find a new file RESULT in the
directory.
– Then apply an external pulse to IRQ2 pin of the IBM PC IO
channel.
– This will again cause the execution of ISR that writes 500 H
bytes into the file.
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 Interrupt Programming
Transfer of control during execution
of an interrupt service routine

Transfer of control for

nested interrupts

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Interrupt Programming

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