8255 (PPI)

Programmable Peripheral Interface.

 Need ??????
 Any microcontroller or a microprocessor has
a limited number of I/O ports, which restricts
the number of I/O devices accessed by or
interfaced to the IC.
 Intel introduced an IC called Programmable
Peripheral Interface (PPI) to check this
drawback of ICs.
 Features of PPI or 8255
 It has 3 I/O ports (24 pins)
 It is compatible to Intel and other
microcontrollers or microprocessors
 It programmable i.e. can be controlled by a
program running on 8051
 Thus 3 I/O ports can be accessed on the
expense of two.
Pin Diagram
 Pin Description
1. PA(0-7): Port A is an I/O port. Its an 8-
bit data output latch/buffer
and an 8-bit data input latch.
2. RD: Read Control is an Active low
input pin. RD is LOW when
CPU (8051) reads data.
3. CS: Chip Select is an Active low
input pin. A LOW on this
pin selects 8255.
 Pin Description
4. GND: This provides the ground for
the IC
5. A0,A1: These pins along with RD,WR,
CS pins control the operation of
8255. User needs to use these
5 pins to program 8255.
Accessing these pins is in the
following way
 Pin Description
6. PC(0-7): Port C is an 8-bit I/O port. Its
lower 4-bits can be programmed
to work in conjunction with PortB
and the upper 4-bits can be
programmed to work in
conjunction with Port A
separately.
7. PB(0-7): Port B is an 8-bit I/O port used
for 8-bit output data latch/buffer
or input data buffer.
 Pin Description
7. Vcc: +5V power supply.
8. D7-D0: Data bus, bidirectional, tristate
lines connected to
system (8051) data lines
9. RESET: Reset is an input pin which
sets the PPI to its default state.
10. WR: Write Enable is an active low
input pin.
11. NC: Pin numbers 1,12,23,24 on a
PLCC package are left
unconnected.
Pin Description (Accessing 8255 using A0,
A1 ,RD ,WR ,CS pins)
 Functional Description
 Data Bus Buffer is a 3-state bidirectional 8-bit
buffer used to interface with system data bus.
 Read/Write and Control Logic controls all of
the internal and external transfer of both data
and control or status words.
 Ports A, B, and C are each 8-bit ports which
can be configured by software. These also
offer a wide range of characteristics to the
system software.
 Operational Description
 8255 can be operated in three modes
 Mode 0(Basic Input Output).
 Mode 1(Strobed Input Output).
 Mode 2(Bi-Directional Bus).
 Any of the 8-bits of port C can be set or
reset. This feature supports control based
software requirements.
 Operational Description

 Mode 0:
 Two 8-bit ports, two 4-bit ports
 Output ports are latched, input ports are

not
 Any port can be input or output

 16 different input output configurations

are possible
 Operational Description
 Mode 1
 Three ports are available as two groups.
 Each port contains one 8- bit data port and one
4- bit control port.
 Both the data ports can either be input or output.
Both the input or output are latched.
 The 4-bit port can be used as both control or
status port.
 Operational Description
 Mode 2:
 Used in group A only.
 8-bit, bidirectional bus port (port A) and 5-bit
control port (port C).
 Both inputs and outputs are latched.
 The 5-bit control port (port C) is used for control
or status for the 8-bit, bidirectional bus (port A)
 Schematic
+5V
10 uFd

U2

31

40
C3

P2.0/A8
21
Latch PPI
VCC
22
EA/VPP
P2.1/A9 23
P2.2/A10 24
P2.3/A11 25 +5V
P2.4/A12 26
P2.5/A13 27 +5V
29 P2.6/A14 28
PSEN P2.7/A15

26
R1 U1
10 K

20
U3 4
9 30 11 2 9 PA0 3
RST ALE/PROG G Q0 A0 PA1

VCC
5 8 2
Q1 A1 PA2

VCC
C2 39 3 6 1
33 pFd 19 P0.0/A D0 38 4 D0 Q2 9 PA3 40
XTAL1 AT89C51 P0.1/A D1 D1 Q3 PA4
37 7 12 39
P0.2/A D2 36 8 D2 Q4 15 34 PA5 38
C1 Y1 P0.3/A D3 35 13 D3 Q5 16 33 D0 PA6 37
33 pFd 18 P0.4/A D4 34 14 D4 Q6 19 32 D1 PA7
11.0592 MHz XTAL2 P0.5/A D5 33 17 D5 Q7 31 D2 18
P0.6/A D6 32 18 D6 30 D3 PB0 19
P0.7/A D7 D7 29 D4 PB1 20
D5 PB2

GND
OC
28 21
D6 PB3
1
P1.0 74LS373/LCC 27
D7 PB4
22
2 10 23

10
P1.1 P3.0/RXD PB5

1
3 11 24
4 P1.2 P3.1/TXD 12 36 PB6 25
5 P1.3 P3.2/INTO 13 P3.6 5 WR PB7
6 P1.4 P3.3/INT1 14 P3.7 RD 14
P1.5 P3.4/TO 8255 PC0
7 15 15
8 P1.6 P3.5/T1 16 PC1 16
P1.7 P3.6/WR 17 PC2 17
P3.7/RD PC3 13
PC4
GND

+5V 12
6 PC5 11
CS PC6 10

RESET
20

PC7

GND
U6
14

35
7
1 2
Vcc

3 A1 Y1 4

Microcontroller 5 A2 Y2 6
8 A3 Y3 9
10 A4 Y4 11
12 A5 Y5 13
A6 Y6
Gnd

7404
Inverter
7
 Assembly Language Program for 8255 Data
Transfer
 ORG 00h
 MOV DPTR,#4003h ;Base address of the the
Control Word Register of
8255
 MOV A,#90h ;PA->input, PB->output,
PC->output
 MOVX @DPTR,A ;Instructing Control register
with Control Word
 BACK:MOV DPTR,#4001h ;Base address of Port B
 MOV A,#055h
 MOVX @DPTR,A ;PB=0x55

 MOV DPTR,#4002h ;Base Address of Port C
 MOV A,#0AAh
 MOVX @DPTR,A ;PC=0xaa
 ACALL DELAY ;Delay to check the o/p
 MOV DPTR,#4001h
 MOV A,#0AAh
 MOVX @DPTR,A
 MOV DPTR,#4002h
 MOV A,#055h
 MOVX @DPTR,A
 ACALL DELAY ;Toggling the outputs
 SJMP BACK ;Keep toggling the
outputs

Cont…
 DELAY:
 MOV R0,#0FFh
 LOOP3:MOV R1,#0FFh
 LOOP2:MOV R2,#0FFh ;to create a delay of
128*128*128*8 machine
cycles
 LOOP1: DJNZ R2,LOOP1
 DJNZ R1,LOOP2
 DJNZ R0,LOOP3
 END ;may not reach
here....