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10-Verilog Timing and Delays

The document discusses different types of delays in Verilog including inertial delay, transport delay, and delays in behavioral modeling. Inertial delay models the resistance and capacitance of a circuit node. Transport delay represents the propagation time of signals from module inputs to outputs. Behavioral modeling only supports minimum, typical, and maximum delay values without rise, fall, or turn-off delays. Specify blocks are used to assign pin-to-pin delays and timing checks.

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216 views25 pages

10-Verilog Timing and Delays

The document discusses different types of delays in Verilog including inertial delay, transport delay, and delays in behavioral modeling. Inertial delay models the resistance and capacitance of a circuit node. Transport delay represents the propagation time of signals from module inputs to outputs. Behavioral modeling only supports minimum, typical, and maximum delay values without rise, fall, or turn-off delays. Specify blocks are used to assign pin-to-pin delays and timing checks.

Uploaded by

SreeSirivella
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PPT, PDF, TXT or read online on Scribd
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Delay Models:

Inertial Delay
The inertia of a circuit node to change
value
Abstractly models the RC circuit seen at
the node
Different types
Input inertial delay
Output inertial delay

2005 Verilog HDL 1


Delay Models:
Transport Delay (Path Delay)
Represents the propagation time of
signals from module inputs to its outputs
Models the internal propagation delays of
electrical elements

2005 Verilog HDL 2


Delays in
Behavioral Modeling
Delays in Verilog
Delay in Behavioral Modeling

Only min:typ:max values can be set


i.e. rise/fall/turnoff delays are not supported
Three categories
Regular delays
Intra-assignment delays
Zero delay

2005 Verilog HDL 4


Procedural Assignment Groups

If a procedure block contains more than one


statement, those statements must be
enclosed within
Sequential begin - end block
Parallel fork - join block

When using begin-end, we can give name to


that group. This is called named blocks.
2005 Verilog HDL 5
module initial_fork_join();
reg clk,reset,enable,data;
initial
begin
$monitor("%g clk=%b reset=%b enable=%b data=%b",
$time, clk, reset, enable, data);
fork
#1 clk = 0;
#10 reset = 0;
#5 enable = 0;
#3 data = 0;
join
#1 $display ("%g Terminating simulation", $time);
$finish; 6

end
Path (Transport ) Delays
in Verilog
Delays in Verilog
Transport Delays in Verilog
 Also called
Pin-to-Pin delay
Path delay
 Gate-level, dataflow, and behavioral delays
Property of the elements in the module (white box)
 Styles: Distributed or Lumped
 Path delay
A property of the module (black box)
Delay from any input to any output port

2005 Verilog HDL 8


Transport Delays in Verilog (cont’d)

2005 Verilog HDL 9


Transport Delays in Verilog (cont’d)

specify block
Assign pin-to-pin delays
Define specparam constants
Setup timing checks in the design

2005 Verilog HDL 10


specify blocks
 Parallel connection
 Syntax:
specify
(<src_field> => <dest_field>) = <delay>;
endspecify

 <src_field> and <dest_field> are vectors of equal


length
 Unequal lengths, compile-time error

2005 Verilog HDL 11


specify blocks (cont’d)
 Full connection
 Syntax:
specify
(<src_field> *> <dest_field>) = <delay>;
endspecify

 No need to equal lengths in <src_field> and


<dest_field>

2005 Verilog HDL 12


specify blocks (cont’d)

2005 Verilog HDL 13


specify blocks (cont’d)

 specparam constants
Similar to parameter, but only inside specify block
Recommended to be used instead of hard-coded delay
numbers

2005 Verilog HDL 14


specify blocks
(cont’d)
 Conditional path
delays
Delay depends on
signal values
Also called State-
Dependent Path
Delay (SDPD)

2005 Verilog HDL 15


specify blocks (cont’d)
Rise, Fall, and Turn-off delays

2005 Verilog HDL 16


specify blocks (cont’d)
Rise, Fall, and Turn-off delays

2005 Verilog HDL 17


specify blocks (cont’d)
Min, Typ, Max delays
 Any delay value can also be specified as
(min:typ:max)

2005 Verilog HDL 18


specify blocks (cont’d)

 Handling x transitions
Pessimistic approach
 Transition to x: minimum possible time
 Transition from x: maximum possible time

2005 Verilog HDL 19


specify blocks (cont’d)

Timing Checks
A number of system tasks defined for this
$setup: checks setup-time of a signal before
an event
$hold: checks hold-time of a signal after an
event
$width: checks width of pulses

2005 Verilog HDL 20


specify blocks (cont’d)
Timing Checks
$setup check
Syntax:
$setup(data_event, reference_event, limit);

2005 Verilog HDL 21


specify blocks (cont’d)
Timing Checks
$hold check
Syntax:
$hold(reference_event, data_event, limit);

2005 Verilog HDL 22


specify blocks (cont’d)
Timing Checks
$width check
Syntax:
$width(reference_event, limit);

2005 Verilog HDL 23


Today Summary
 Delays
Models
 Inertial (distributed and lumped delay)
 Transport (path/pin-to-pin delay)
Types
 Rise/Fall/Turn-off
 Min/Typ/Max Values
Delays in Verilog
 Syntax and other common features
 Gate-Level and Dataflow Modeling
 Behavioral Modeling
2005 Verilog HDL 24
Other Notes

Homework 9
Chapter 10:
All exercises
Due date: Sunday, Day 11th

2005 Verilog HDL 25

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