10-Verilog Timing and Delays
10-Verilog Timing and Delays
Inertial Delay
The inertia of a circuit node to change
value
Abstractly models the RC circuit seen at
the node
Different types
Input inertial delay
Output inertial delay
end
Path (Transport ) Delays
in Verilog
Delays in Verilog
Transport Delays in Verilog
Also called
Pin-to-Pin delay
Path delay
Gate-level, dataflow, and behavioral delays
Property of the elements in the module (white box)
Styles: Distributed or Lumped
Path delay
A property of the module (black box)
Delay from any input to any output port
specify block
Assign pin-to-pin delays
Define specparam constants
Setup timing checks in the design
specparam constants
Similar to parameter, but only inside specify block
Recommended to be used instead of hard-coded delay
numbers
Handling x transitions
Pessimistic approach
Transition to x: minimum possible time
Transition from x: maximum possible time
Timing Checks
A number of system tasks defined for this
$setup: checks setup-time of a signal before
an event
$hold: checks hold-time of a signal after an
event
$width: checks width of pulses
Homework 9
Chapter 10:
All exercises
Due date: Sunday, Day 11th