Digital

Fundamentals
Tenth Edition

Floyd

Chapter 9

© 2009 Pearson Education,©Upper

2008 Pearson Education
Floyd, Digital Fundamentals, 10th ed Saddle River, NJ 07458. All Rights Reserved
 Summary
Basic Shift Register Operations
A register is a digital circuit with two basic functions:
1. data storage, and
2. data movement
The storage capability of a register makes it an important
type of memory device.

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Summary
Basic Shift Register Operations
A shift register is an arrangement of flip-flops with
important applications in storage and movement of data.
Some basic data movements are illustrated here.
Data in

Data in Data out Data out Data in Data out

Serial in/shift right/serial out Serial in/shift left/serial out Parallel in/serial out

Data in

Data in

Data out Data out

Serial in/parallel out Parallel in/parallel out Rotate right Rotate left

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Summary
Serial-in/Serial out Shift Register
Shift registers are available in IC form or can be
constructed from discrete flip-flops as is shown here with a
five-bit serial-in serial-out register.
Each clock pulse will move an input bit to the next flip-
flop. For example, a 1 is shown as it moves across.

FF0 FF1 FF2 FF3 FF4

Serial 1 1 1 1 1 1 Serial
data D0 Q0 D1 Q1 D2 Q2 D3 Q3 D4 Q4 data
input output

C C C C C

CLK
CLK

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Summary
Serial-in/Serial out Shift Register Example

For example, assume the binary number 1011 is loaded

sequentially, one bit at each clock pulse.
After 4 clock pulses, the last data bit is available at Q3
output.

FF0
FF0 FF1 FF2
FF2 FF3
FF3
Serial X
0
1 1
0 10
1 10 11
data D
D00 Q
Q00 D
D11 Q
Q11 D
D22 Q
Q22 D
D33 Q
Q33
input
C
C C
C C
C C
C

CLK
CLK

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Summary
Serial-in/Serial out Shift Register Example

If you want to get the data out of the register, the bits
must be shifted out serially and taken off the Q3 output.

Read out 10
FF0 FF1 FF2 FF3
Serial x1 1 1 0 1
data D0 Q0 D1 Q1 D2 Q2 D3 Q3
input
C C C C

CLK
CLK

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Summary
Serial-in/Serial out Shift Register Wave Form Example
Show the states of the 5-bit register in Figure for the
specified data input and clock waveforms. Assume that
the register is initially cleared (all 0s).

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Summary
Serial-in/Serial out Shift Register Wave Form Solution

1 1 0 1 0

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Summary
SERIAL IN/PARALLEL OUT SHIFT REGISTERS
An application of shift registers is conversion of serial
data to parallel form.
For example, assume the binary number 1011 is loaded
sequentially, one bit at each clock pulse.
After 4 clock pulses, the data is available at the parallel output.

FF0
FF0 FF1 FF2
FF2 FF3
FF3
Serial X
0
1 1
0 10
1 10 11
data D
D00 Q
Q00 D
D11 Q
Q11 D
D22 Q
Q22 D
D33 Q
Q33
input
C
C C
C C
C C
C

CLK
CLK

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Summary
The 74HC164A Shift Register
The 74HC164A is a CMOS 8-bit serial in/parallel out shift
register. VCC can be from +2.0 V to +6.0 V.
(9)
CLR
(8)
CLK
(1)
Serial  A
(2) R R R R R R R R
  B
inputs C C C C C C C C

S S S S S S S S

(3) (4) (5) (6) (10) (11) (12) (13)

Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7

One of the two serial data inputs may be used as an active HIGH
enable to gate the other input.
If no enable is needed, the other serial input can be connected to VCC.
The 74HC164A has an active LOW asynchronous clear. Data is
entered on the leading-edge of the clock.
Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Summary
Waveforms for the 74HC164A
Sample waveforms for CLR

the 74HC164A are Serial 

A

shown. Notice that B   B

inputs
acts as an active HIGH CLK
enable for the data on Q0

A as discussed. Q1

As with CMOS Q2

devices, unused inputs Q3

should always be Outputs
Q
connected to a logic
4

Q
level; unused outputs 5

Q
should be left open. 6

Q7

Clear Clear

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Summary
Parallel in/Serial out Shift Register
Shift registers can be used to convert parallel data to serial
form. A logic diagram for this type of register is shown:
D0 D1 D2 D3
1 1 0
0 SHIFT/LOAD
1 1 0 1 1

G1 G5 G2 G6 G3 G7 G4

Q3 Serial
D Q0 D Q1 D Q2 D
data out
C C C C

FF0 FF1 FF2 FF3

CLK

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Summary
Parallel in/Serial out Shift Register
Shift registers can be used to convert parallel data to serial
form. A logic diagram for this type of register is shown:
D0 D1 D2 D3

1 SHIFT/LOAD
0 0 0 0

G1 G5 G2 G6 G3 G7 G4

Q3 Serial
D Q0 D Q1 D Q2 D
C 1 C 0 C 1 C 0 data out

FF0 FF1 FF2 FF3

CLK

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Summary
Parallel in/Serial out Shift Register Example
Show the data-out put waveform for a 4-bit register with
the parallel input data and the clock and SHIFT/LOAD
waveforms given in Figure • On clock pulse 1, the parallel data
(D0D1,D2D3 = 1010) are loaded into the
register making Q3, = 0.
• Clock pulse 2 : the 1 from Q2 is shifted
onto Q3.
• Clock pulse 3 : the 0 is shifted onto Q3
• Clock pulse 4 : the last data bit (1) is
shifted onto Q3; and
• Clock pulse 5 : all data bits have been
shifted out, and only 1s remain in the
register (assuming the D input remains a
1).

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Summary
The 74HC165 Shift Register
The 74HC165 is a CMOS 8-bit parallel in/serial out shift
register. The logic symbol is shown:

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Summary
The 74HC165 Shift Register
The 74HC165 is a CMOS 8-bit parallel in/serial out shift
register. The logic symbol is shown:
D0 D1 D2 D3 D4 D5 D6 D7
(11) (12) (13) (14) (3) (4) (5) (6)
(1) (9)
SH/LD (10) SRG 8 Q7
SER
(15)
CLK INH (2) (7)
CLK C Q7

The clock (CLK) and clock inhibit (CLK INH) lines are connected to a
common OR gate, so either of these inputs can be used as an active-
LOW clock enable with the other as the clock input. Data is loaded
asynchronously when SH/LD is LOW and moved through the register
synchronously when SH/LD is HIGH and a rising clock pulse occurs.

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Summary
The 74HC165 Shift Register Timing Diagram

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Summary
Universal Shift Register

A universal shift register has both serial and parallel

input and output capability. The 74HC194 is an example
of a 4-bit bidirectional universal shift register.

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Summary
Universal Shift Register

A universal shift register has both serial and parallel

input and output capability. The 74HC194 is an example
of a 4-bit bidirectional universal shift register.
D0 D1 D2 D3

(3) (4) (5) (6)

(1)
CLR SRG 4
(9)
S0
(10)
S1
(2)
SR SER
(7)
SL SER
(11)
CLK C
(15) (14) (13) (12)

Q0 Q1 Q2 Q3
Sample waveforms are
on the following slide…

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Summary
Universal Shift Register
CLK

Mode S0
control
inputs S1

CLR

Serial SR SER
data
inputs SL SER

D0
Parallel D1
data
inputs D2
D3

Q0

Q1
Parallel
outputs
Q2

Q3
Shift right Shift left Inhibit
Clear Load Clear

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Summary
Shift Register Counters
Shift registers can form useful counters by recirculating
a pattern of 0’s and 1’s. Two important shift register
counters are the Johnson counter and the ring counter.
FF0 FF1 FF2 FF3
The Johnson counter can D0 Q0 D1 Q1 D2 Q2 D3 Q3

be made with a series of D C C C C

flip-flops Q3 Q3

CLK

… or with a series of J-K J0

FF0

Q0 J1
FF1

Q1 J2
FF2

Q2 J3
FF3

Q3
Q3

flip flops. Here Q3 and Q3

C C C C
are fed back to the J and K K0 Q0 K1 Q1 K2 Q2 K3 Q3
Q3

inputs with a “twist”.

CLK

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Summary
Johnson Counter
Redrawing the same Johnson counter (without the clock
shown) illustrates why it is sometimes called as a “twisted-
ring” counter.
FF0

J0 Q0

“twist” C

K0 Q0

Q3
Q3
Q3

Q3

K1

J1
C
FF3

FF1
C

Q1

Q1
J3

K3

2 Q 2 K

2 Q 2 J

FF2

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Summary
Johnson Counter
The Johnson counter is useful when you need a sequence
that changes by only one bit at a time but it has a limited
number of states (2n, where n = number of stages).
The first five counts for a 4-bit Johnson counter that is
initially cleared are: CLK Q 0 Q1 Q2 Q3
0 0 0 0 0
1 1 0 0 0
2 1 1 0 0
3 1 1 1 0
4 1 1 1 1
5 0 1 1 1
6 0 0 1 1
What are the remaining 3 states? 7 0 0 0 1

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Summary
Ring Counter
The ring counter can also be implemented with either D
flip-flops or J-K flip-flops.
FF0 FF1 FF2 FF3

Here is a 4-bit ring counter D0 Q0 D1 Q1 D2 Q2 D3 Q3

Q3

constructed from a series C C C C

of D flip-flops. Notice the

feedback. CLK

FF0 FF1 FF2 FF3

Like the Johnson counter, J0 Q0 J 1 Q1 J 2 Q2 J 3 Q3

Q3

it can also be implemented C C C C

with J-K flip flops. K0 Q0 K1 Q1 K2 Q2 K3 Q3

Q3

CLK

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Summary
Ring Counter
Redrawing the Ring counter (without the clock shown)
shows why it is a “ring”.
FF0
The disadvantage to this counter J0 Q0

is that it must be preloaded with C

the desired pattern (usually a K0 Q0

single 0 or 1) and it has even

fewer states than a Johnson

Q3
Q3
Q3

Q3

K1

J1
C
counter (n, where n = number of
FF3

FF1
C
3

K3

Q1

Q1
J
flip-flops.
On the other hand, it has the 2 Q 2 K

advantage of being self-decoding C

with a unique output for each state. 2 Q 2 J

FF2

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Summary
Ring Counter
A common pattern for a ring counter is to load it with a single 1 or a
single 0. The waveforms shown here are for an 8-bit ring counter
with a single 1.
CLK 1 2 3 4 5 6 7 8 9 10

Q0

Q1

Q2

Q3

Q4

Q5

Q6

Q7

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Summary
Shift Register Applications
Shift registers can be used to delay a digital signal by a
predetermined amount.
An 8-bit serial in/serial out shift register has a 40 MHz
clock. What is the total delay through the register?

A SRG 8 Q7
Data in Data out
B
Q7
The delay for each clock CLK
40 MHz
C

is 1/40 MHz = 25 ns
25 ns

The total delay is CLK

8 x 25 ns = 200 ns
Data in

Data out
td = 200 ns

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Summary
Shift Register Applications
Data bus
A UART (Universal Asynchronous
Receiver Transmitter) is a serial-to-
Buffers
parallel converter and a parallel to
serial converter.
Transmitter Receiver
UARTs are commonly used in small data register data register

systems where one device must

communicate with another. Parallel Transmitter Receiver
CLK CLK
data is converted to asynchronous shift register shift register

serial form and transmitted. The Serial data out Serial data in
serial data format is:
Start
D7 D6 D5 D4 D3 D2 D1 D0 Stop Bits (1)
Bit (0)
t

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Summary
Keyboard Encoder

The keyboard encoder is an example of where a ring

counter is used in a small system to encode a key press.
Two 74HC195 shift registers are connected as an 8-bit
ring counter preloaded with a single 0. As the 0
circulate in the ring counter, it “scans” the keyboard
looking for any row that has a key closure. When one is
found, a corresponding column line is connected to that
row line. The combination of the unique column and
row lines identifies the key. The schematic is shown on
the following slide…

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Power on LOAD
SH/LD +V CC
Ring counter

D0 D1 D2 D3 D4 D5 D6 D7
J J
K SRG 4 K SRG 4
CLK 74HC195 74HC195
(5 kHz) C C +V
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7

Clock inhibit

1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
ROW encoder COLUMN encoder
74HC147 74HC147
1 2 4 1 2 4

Switch closure
Q Q D0 D1 D2 D3 D4 D5
C
Key code register
74HC174
C C
Q0 Q1 Q2 Q3 Q4 Q5

Q
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To ROMEducation, Upper Saddle River, NJ 07458.
© 2008All
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RightsEducation
Reserved
 1. The shift register that would be used to delay serial data by
4 clock periods is Data in

a. c.
Data in Data out Data out

Data in

b. Data in d.

Data out Data out

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
© 2008 Pearson Education
 2. The circuit shown is a
a. serial-in/serial-out shift register
b. serial-in/parallel-out shift register
c. parallel-in/serial-out shift register
d. parallel-in/parallel-out shift register
D0 D1 D2 D3

SHIFT/LOAD

G4 G1 G5 G2 G6 G3

Serial
D0 Q0 D1 Q1 D2 Q2 D3 Q3 data
out

C C C C

CLK

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
© 2008 Pearson Education
 3. If the SHIFT/LOAD line is HIGH, data
a. is loaded from D0, D1, D2 and D3 immediately
b. is loaded from D0, D1, D2 and D3 on the next CLK
c. shifted from left to right on the next CLK
d. shifted from right to left on the next CLK
D0 D1 D2 D3

SHIFT /LOAD

G4 G1 G5 G2 G6 G3

Serial
D0 Q0 D1 Q1 D2 Q2 D3 Q3 data
out

C C C C

CLK
Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
© 2008 Pearson Education
 4. A 4-bit parallel-in/parallel-out shift register will store
data for
a. 1 clock period
b. 2 clock periods
c. 3 clock periods
d. 4 clock periods

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
© 2008 Pearson Education
 5. The 74HC164 (shown) has two serial inputs. If data is
placed on the A input, the B input
a. could serve as an active LOW enable
b. could serve as an active HIGH enable
c. should be connected to ground
d. should be left open
(9)
CLR
(8)
CLK
(1)
Serial  A
(2) R R R R R R R R
  B
inputs C C C C C C C C

S S S S S S S S

(3) (4) (5) (6) (10) (11) (12) (13)

Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
© 2008 Pearson Education
 6. An advantage of a ring counter over a Johnson counter is
that the ring counter
a. has more possible states for a given number of flip-flops
b. is cleared after each cycle
c. allows only one bit to change at a time
d. is self-decoding

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 7. A possible sequence for a 4-bit ring counter is
a. … 1111, 1110, 1101 …
b. … 0000, 0001, 0010 …
c. … 0001, 0011, 0111 …
d. … 1000, 0100, 0010 …

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 8. The circuit shown is a
a. serial-in/parallel-out shift register
b. serial-in/serial-out shift register
c. ring counter
d. Johnson counter
FF0 FF1 FF2 FF3
Q3
J0 Q0 J1 Q1 J2 Q2 J3 Q3

C C C C

Q3
K0 Q0 K1 Q1 K2 Q2 K3 Q3

CLK

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 9. Assume serial data is applied to the 8-bit shift register
shown. The clock frequency is 20 MHz. The first data bit

will show up at the output in

a. 50 ns
b. 200 ns
c. 400 ns
d. 800 ns
A SRG 8 Q7
Data in Data out
B
CLK Q7
C
20 MHz

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
© 2008 Pearson Education
 10. For transmission, data from a UART is sent in
a. asynchronous serial form
b. synchronous parallel form
c. can be either of the above
d. none of the above

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
© 2008 Pearson Education
 Answers:
1. a 6. d
2. c 7. d
3. c 8. d
4. a 9. c
5. b 10. a

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved