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Introduction To Fpgas

The document provides an introduction to FPGA architecture. It discusses the basic components of FPGA logic blocks including lookup tables (LUTs), flip flops (FFs), and programmable routing. It explains how LUTs can implement different logic functions using SRAM cells and multiplexers. The document also discusses FPGA design flow and considerations in logic block architecture such as LUT size, cluster size, and use of hard blocks like memory, DSP, and processor blocks.

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16 views25 pages

Introduction To Fpgas

The document provides an introduction to FPGA architecture. It discusses the basic components of FPGA logic blocks including lookup tables (LUTs), flip flops (FFs), and programmable routing. It explains how LUTs can implement different logic functions using SRAM cells and multiplexers. The document also discusses FPGA design flow and considerations in logic block architecture such as LUT size, cluster size, and use of hard blocks like memory, DSP, and processor blocks.

Uploaded by

dhamodar reddy
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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Introduction to FPGAs

Outline
Architecture
Logic
Routing
I/O

State-of-the-art: Xilinx Virtex 7


FPGA Architecture

Programmable Logic

Programmable Routing

3
Logic: Lookup Tables

LUT FF

2K 2K:1
LUT FF

SRAM MUX

LUT FF

LUT FF

Slice/Cluster

4
Look-up Table
2K SRAM Cells

K
22 different functions

2K 2K:1

SRAM MUX 2K:1 MUX


K-levels of 2:1 muxes

5
Look-up Table: 2-inputs
22 SRAM Cells

2
2
2 different functions

22 22:1

SRAM MUX 22:1 MUX


2-levels of 2:1 muxes

6
Look-up Table: 2-input NAND
4 SRAM Cells
6 transistors each

1 4:1 MUX
1 4:1
~12 transistors
1 MUX

0
~40 Transistors
2

7
Look-up Table: 2-input NAND

HUGE!

1
1 4:1

1 MUX

0
2

40 Transistors 4 Transistors
8
Design Flow: FPGA

Benchmark Circuits HDL

Logic Synthesis

FPGA Architecture Technology Mapping

Pack, Place & Route

FPGA Area, Power, Speed

9
Architecture-level studies
Depth of the CAD flow
Quality of the CAD tools
Benchmark circuits
Quality of tools used to measure performance
LOGIC BLOCK ARCHITECTURE
Logic: Soft

Programmable
Logic Blocks

12
Logic: Hard Blocks

Memory
Blocks

13
Logic: Hard Blocks

DSP
Blocks

14
Logic: Lookup Tables

LUT FF

2K 2K:1
LUT FF

SRAM MUX

LUT FF

LUT FF

Slice/ Cluster

15
Design decisions
LUT size
Number of LUTs per cluster
Inputs/Outputs to/from each cluster
Area and Speed
No. of Logic Blocks vs.
Logic Block Functionality

LUT size increases exponentially with K


Routing tracks surrounding logic increases
with the number of input pins
Total FPGA area vs. LUT size
Terminology
Basic logic element (BLE) LUT FF

Cluster
Size grows quadratically LUT FF

Local interconnect
Fewer inputs (shared) LUT FF

LUT FF
LUTs on critical path & LUT delay
vs LUT size

Functionality increases=> fewer logic blocks on critical path


=> internal delay increases
Critical path: Function of LUT and
Cluster size

Diminishing returns beyond


LUT6 and cluster size 3,4
HETEROGENEOUS BLOCKS
Choice of functions
Which function?
Ratio of special function
to generic logic?
What to do with special
function blocks when
they are not used?
Hard blocks
FFs (set, reset, enable, load,)
Add, sub, carry logic,
Use LUTs as memories
Block RAMs/ ROMs, FIFOs
Multipliers (fracturable)
Processors
Challenge
Performance, power, area
As compared to ASICs
Introduce other hard blocks
Floating point units, etc.
Shadow logic

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