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Computer Arithmetic: Part III: Floating-Point Arithmetic

The document discusses floating-point arithmetic, including: 1) Addition and subtraction of floating-point numbers by matching exponents, adding or subtracting significands, and normalizing results. Overflow and underflow may occur. 2) Multiplication by adding exponents, multiplying significands, and normalizing. 3) Division by subtracting exponents, dividing significands, and normalizing. 4) The importance of guard bits in floating-point registers to improve rounding accuracy during intermediate calculations.

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26 views19 pages

Computer Arithmetic: Part III: Floating-Point Arithmetic

The document discusses floating-point arithmetic, including: 1) Addition and subtraction of floating-point numbers by matching exponents, adding or subtracting significands, and normalizing results. Overflow and underflow may occur. 2) Multiplication by adding exponents, multiplying significands, and normalizing. 3) Division by subtracting exponents, dividing significands, and normalizing. 4) The importance of guard bits in floating-point registers to improve rounding accuracy during intermediate calculations.

Uploaded by

tesfu
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© © All Rights Reserved
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Lecture 6

Computer Arithmetic
Part III: Floating-Point Arithmetic

Zelalem Birhanu, AAiT 1


Last lecture:

Integer Arithmetic
Multiplication and Division

Floating-Point Representation
IEEE 754

Zelalem Birhanu, AAiT 2


In this lecture:

Floating-Point Arithmetic
Addition/Subtraction
Multiplication
Division

Zelalem Birhanu, AAiT 3


Review

Exercise
What is the value (in decimal) of the following IEEE 754
floating point encoded number?

1 01111110 01000000000000000000000

Sign: Negative
Exponent:126-127 = -1
Significand:1.01

. = + = .

Zelalem Birhanu, AAiT 4


Addition

Decimal Addition
e.g.
2.625 103 + 3 102

2.625 103 0.3 103



2.925 103

Zelalem Birhanu, AAiT 5


Additioncntd

Binary addition/subtraction

Follow similar steps


Check for zeros
Match exponents (Align the significands)
Shift significand of smaller exponent to the right and increment
exponent
Add/Subtracts significands
Normalize result

Zelalem Birhanu, AAiT 6


Additioncntd
Implied bit FPU Registers
Example (. + . )
. = . 0 129 1011010

. = . 0 128 1000000

Match 0 129 1011010


Note:
Exponent in decimal exponents 0 129 0100000
Significand in binary
Add 0 129 1111010
significands

Normalize 0 129 1111010


(already normalized)

. = . = .

Zelalem Birhanu, AAiT 7


Additioncntd
Implied bit
Exercise (. + . )
. = . 0 126 100

. = . 1 125 100

Match 0 126 100


Note:
Exponent in decimal exponents 1 126 010
Significand in binary
Add 0 126 010
significands

Normalize 0 125 100

. = . = .

Zelalem Birhanu, AAiT 8


Additioncntd

During arithmetic operations overflow or


underflow may occur
Exponent overflow: When positive exponent exceeds
maximum possible exponent value (e.g. 129 in IEEE 754
single precision)

Exponent underflow: When negative exponent is less than


minimum possible exponent value (e.g. -129 in IEEE 754
single precision)

Significand overflow: Carry out of the MSB of a result (e.g.


while adding two significands)

Significand underflow: When aligning significands digits may


flow off the right end of the significand
Zelalem Birhanu, AAiT 9
Multiplication

Check for zeros


If either operand is zero result is zero
Add exponents and subtract bias value (127 in
case of IEEE 754)
Multiply significands
Normalize
Compute sign bit (simple exclusive-or)

Zelalem Birhanu, AAiT 10


Multiplicationcntd
Implied bit FPU Registers
Example (. . )
. = . 0 129 1011010

. = . 0 128 1000000

Note: Add 0 (129+128-127)=130 000000


Exponent in decimal exponents
Significand in binary
Multiply 0 130 10110100000
significands

Normalize 0 130 10110100000


(already normalized)

. = . = .

Zelalem Birhanu, AAiT 11


Multiplicationcntd
Implied bit
Exercise (. . )
. = . 0 126 100

. = . 1 125 100

Add 0 (126+125-127)=124 000000


Note: exponents
Exponent in decimal
Multiply 0 124 1000
Significand in binary
significands
Normalize 0 124 1000
(already normalized)

Compute 1 124 1000


sign bit

. = . = .

Zelalem Birhanu, AAiT 12


Division

Check for zeros


If divisor is 0 report error, if dividend is 0 report result
as 0
Subtract divisor exponent from dividend
exponent and add bias value (127 in case of IEEE
754)
Divide significands
Normalize
Compute sign bit

Zelalem Birhanu, AAiT 13


Divisioncntd
Implied bit FPU Registers
Example (. . )
. = . 0 129 1011010

. = . 0 128 1000000

Note: Subtract 0 (129-128+127)=128 000000


Exponent in decimal exponents
Significand in binary
Divide 0 128 1011010
significands

Normalize 0 128 1011010


(already normalized)

. = . = .

Zelalem Birhanu, AAiT 14


Divisioncntd
Implied bit
Exercise (. (. ))
. = . 0 126 100

. = . 1 125 100

Subtract 0 (126-125+127)=128 000000


Note: exponents
Exponent in decimal
Divide 0 128 10
Significand in binary
significands
Normalize 0 128 10
(already normalized)

Compute 1 128 10
sign bit

. = . = .

Zelalem Birhanu, AAiT 15


Guard bits and rounding

Registers inside a floating-point unit (FPU) are usually


wider than bits used to represent floating-point
numbers (e.g. x86 FPU has 8 registers with 80 bits
each)

The registers have additional bits (guard bits) used


during intermediate operations to improve rounding
accuracy.

E.g. Assume decimal floating-point representation with 3 digit


significand, and 2 guard bits.
Compute the addition 2.56 100 + 2.34 102
Zelalem Birhanu, AAiT 16
With guard bits

Match exponents 2.56 100 = 0.0256 102


Under flow (use
guard bits)

Add significands0.0256 + 2.3400 = 2.3656


The sum is given as 2.3656 102

Round sum2.37 102

Zelalem Birhanu, AAiT 17


Without guard bits

Match exponents 2.56 100 = 0.0256 102 = 0.02 102

Under flow (drop


two digits)

Add significands0.02 + 2.34 = 2.36


The sum is given as 2.36 102

Zelalem Birhanu, AAiT 18


More Readings

1. Computer Architecture and Organization,


William Stallings, 8th edition (chapter 9)
2. Computer Organization and Design, David A.
Patterson, 4th edition (section 3.5)

Zelalem Birhanu, AAiT 19

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