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Arith 3

1) Arithmetic-Logic Units (ALUs) perform arithmetic and logical operations and are built using basic logic gates like AND, OR, and NOT. 2) An ALU can be tailored to support the operations in the MIPS instruction set by allowing different configurations for addition, subtraction, AND, OR, and comparisons using multiplexors and control lines. 3) The output of an operation like subtraction can be used to perform comparisons like less-than by checking the most significant bit or a zero check can test for equality.

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0% found this document useful (0 votes)
28 views18 pages

Arith 3

1) Arithmetic-Logic Units (ALUs) perform arithmetic and logical operations and are built using basic logic gates like AND, OR, and NOT. 2) An ALU can be tailored to support the operations in the MIPS instruction set by allowing different configurations for addition, subtraction, AND, OR, and comparisons using multiplexors and control lines. 3) The output of an operation like subtraction can be used to perform comparisons like less-than by checking the most significant bit or a zero check can test for equality.

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Lizzie
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Arithmetic-Logic Units

CPSC 321 Computer Architecture


Andreas Klappenecker
Logic Gates

AND gate

OR gate

NOT gate
Logic Gates

NOR gate

NAND gate

XOR gate
Half Adder
a s
b
a b c s c
0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0
Full Adder
cin a b cout s
0 0 0 0 0
0 0 1 0 1
s=cin xor a xor b 0 1 0 0 1
0 1 1 1 0
cout=ab+cin(a xor b) 1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1
Full Adder

cin
s
a
b
cout

s=cin xor a xor b cout = ab+cin(a xor b)


Ripple Carry Adder
Ripple Carry Adders
Each gates causes a delay
our example: 3 gates for carry generation
book has example with 2 gates
Carry might ripple through all n adders
O(n) gates causing delay
intolerable delay if n is large
Carry lookahead adders
Faster Adders
cin a b cout s
cout=ab+cin(a xor b)
0 0 0 0 0
=ab+acin+bcin
0 0 1 0 1
=ab+(a+b)cin 0 1 0 0 1
= g + p cin 0 1 1 1 0
Generate 1 0 0 0 1
g = ab 1 0 1 1 0
Propagate 1 1 0 1 0
p = a+b 1 1 1 1 1
Fast Adders
Iterate the idea, generate and propagate
ci+1 = gi + pici
= gi + pi(gi-1 + pi-1 ci-1)
= gi + pigi-1+ pipi-1ci-1
= gi + pigi-1+ pipi-1gi-2 ++ pipi-1 p1g0
+pipi-1 p1p0c0
Two level AND-OR circuit
Carry is known early!
Carry Lookahead Adders
Based on the previous identity
Fast because critical path is shorter
O(log n) gate delays [assuming 2-input gates]
More complex to implement
Design is less regular
Layout of one bit adder cells depend on i
Compromise
couple blocks of carry lookahead adders
Building an ALU
Binvert Operation

Addition CarryIn

Subtraction a
0

AND 1
Result

OR
b 0 2

CarryOut

What is missing?
Tailoring the ALU to the MIPS
Need to support the set-on-less-than instruction (slt)
remember: slt is an arithmetic instruction
produces 1 if rs < rt and 0 otherwise
use subtraction: (a-b) < 0 implies a < b
Need to support test for equality (beq $t5, $t6, $t7)
use subtraction: (a-b) = 0 implies a = b
SLT
Binvert Operation
Determine a<b CarryIn

Calculate b-a a
0
If MSB equals
1, then a<b 1
Result

0, then a>=b
b 0 2
Changes? 1

Operation less than


Output of subtraction CarryOut

Overflow
a. CarryOut

SLT
Binvert Operation
CarryIn
4 ops
subtraction a
0
output available
Connect
1

MSB set Result

output b 0 2

1
w/ LSB less
Less 3

Set

Overflow
Overflow
detection
b.
Binvert CarryIn Operation

LSB indicates a0 CarryIn

whether a<b
b0 ALU0 Result0
Less
CarryOut

0 if false a1 CarryIn
b1 ALU1 Result1

1 if true
0 Less
CarryOut

a2 CarryIn
b2 ALU2 Result2
0 Less
CarryOut

CarryIn

a31 CarryIn Result31


b31 ALU31 Set
0 Less Overflow
Bnegate Operation

Test for equality a0


b0
CarryIn
ALU0
Result0
Less
CarryOut

Notice control lines:


a1 CarryIn Result1
b1 ALU1
0 Less
000 = and CarryOut Zero

001 = or
010 = add a2
b2
CarryIn
ALU2
Result2
0 Less
110 = subtract CarryOut

111 = slt

Note: zero is a 1 when the result is zero! a31 CarryIn


Result31
b31 ALU31 Set
0 Less Overflow
Conclusions
We can build an ALU to support the MIPS instruction set
key idea: use multiplexor to select the output we want
we can efficiently perform subtraction using twos complement
we can replicate a 1-bit ALU to produce a 32-bit ALU
Important points about hardware
all of the gates are always working
the speed of a gate is affected by the number of inputs to the gate
the speed of a circuit is affected by the number of gates in series
(on the critical path or the deepest level of logic)
We focused on basic principles. We noted that
clever changes to organization can improve performance
(similar to using better algorithms in software)
faster addition, next time: faster multiplication

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