ELEVATOR CONTROL SYSTEM

USING
FPGA

SUBMITTED BY:
ADITYA GUPTA(15102031)
SNEHA YADAV(15102194)
 ABSTRACT

The aim of the project is to design and implement an Elevator/Lift Controller using Verilog
hardware descriptive language (HDL). The Elevator Controller is a device used to control a lift
motion and to indicate the direction of motion, and the present floor level, etc. The device
controls the lift motion by means of accepting the floor level as input and generate control
signals (for control the lift motion) as output. The elevator controller is based on the concept
of finite state machine technology. According to the FSM technology the elevator process
can be defined with the help of different states. In the FSM technology there is a change from
one state to another state likewise in the elevator there will be a change from one floor to
another. Every possible way is assigned a path and the implemented based on FSM concept
to write the program code for elevator controller. The whole program is designed in such a
way that there are desirable switches in each floor and also inside the elevator to control the
user commands. The design includes a simple scheme that aims at a good speed of
response without requiring any extra logic circuitry.
 What is an FPGA?

Field Programmable Gate Arrays (FPGAs) are semiconductor

devices that are based around a matrix of configurable logic
blocks (CLBs) connected via programmable interconnects. FPGAs
can be reprogrammed to desired application or functionality
requirements after manufacturing. This feature distinguishes FPGAs
from Application Specific Integrated Circuits (ASICs), which are
custom manufactured for specific design tasks. Although one-time
programmable (OTP) FPGAs are available, the dominant types are
SRAM based which can be reprogrammed as the design evolves.
 Advantage of FPGA over PLCs

Many industrial and control applications are running through conventional

PLC technology adequately because PLC provides flexibility, lower cost
and security compared to other control techniques, but still a more
powerful alternative is needed.
In recent years, FPGAs becomes the best replacement of PLC to
implement control algorithms in industrial, digital signal processing, video
and audio applications and as well to perform control tasks. The basic
dilemma of FPGAs is that it requires an expertise in control automation
applications. In this project, an efficient methodology is proposed to
implement PLC state diagram on FPGA using Xilinx StateCAD tool. Three
level efficient elevator control system is designed which can be used for
different elevator control system having different number of floors. Simply
changing the state diagram, VERILOG HDL(Hardware Description
Language) code is generated and used in XILINX ISE 7.1i to implement
control system on FPGA
Spartan-3. StateBench simulator is used to simulate results of proposed
control system.
 FPGA Applications

Due to their programmable nature, FPGAs are an ideal fit for many different markets. As the industry leader, Xilinx
provides comprehensive solutions consisting of FPGA devices, advanced software, and configurable, ready-to-use
IP cores for markets and applications such as:
Aerospace & Defense - Radiation-tolerant FPGAs along with intellectual property for image processing,
waveform generation, and partial reconfiguration for SDRs.
ASIC Prototyping - ASIC prototyping with FPGAs enables fast and accurate SoC system modeling and
verification of embedded software
Audio - Xilinx FPGAs and targeted design platforms enable higher degrees of flexibility, faster time-to-market,
and lower overall non-recurring engineering costs (NRE) for a wide range of audio, communications, and
multimedia applications.
Automotive - Automotive silicon and IP solutions for gateway and driver assistance systems, comfort,
convenience, and in-vehicle infotainment. - Learn how Xilinx FPGA's enable Automotive Systems
Broadcast & Pro AV - Adapt to changing requirements faster and lengthen product life cycles with Broadcast
Targeted Design Platforms and solutions for high-end professional broadcast system.
 VERILOG-HDL

Hardware description languages such as Verilog are similar to software programming

languages because they include ways of describing the propagation time and signal strengths
(sensitivity). There are two types of assignment operators; a blocking assignment (=), and a non-
blocking (<=) assignment. The non-blocking assignment allows designers to describe a state-
machine update without needing to declare and use temporary storage variables. Since these
concepts are part of Verilog's language semantics, designers could quickly write descriptions of
large circuits in a relatively compact and concise form. At the time of Verilog's introduction (1984),
Verilog represented a tremendous productivity improvement for circuit designers who were already
using graphical schematic capture software and specially written software programs to document
and simulate electronic circuits.
The designers of Verilog wanted a language with syntax similar to the C programming language,
which was already widely used in engineering software development. Like C, Verilog is case-
sensitive and has a basic preprocessor (though less sophisticated than that of ANSI C/C++). Its control
flow keywords (if/else, for, while, case, etc.) are equivalent, and its operator precedence is
compatible with C. Syntactic differences include: required bit-widths for variable declarations,
demarcation of procedural blocks (Verilog uses begin/end instead of curly braces {}), and many
other minor differences. Verilog requires that variables be given a definite size. In C these sizes are
assumed from the 'type' of the variable (for instance an integer type may be 8 bits).
 A Verilog design consists of a hierarchy of modules. Modules encapsulate design
hierarchy, and communicate with other modules through a set of declared input, output,
and bidirectional ports. Internally, a module can contain any combination of the
following: net/variable declarations (wire, reg, integer, etc.), concurrent and
sequential statement blocks, and instances of other modules (sub-hierarchies).
Sequential statements are placed inside a begin/end block and executed in sequential
order within the block. However, the blocks themselves are executed concurrently,
making Verilog a dataflow language.
Verilog's concept of 'wire' consists of both signal values (4-state: "1, 0, floating,
undefined") and signal strengths (strong, weak, etc.). This system allows abstract
modeling of shared signal lines, where multiple sources drive a common net. When a wire
has multiple drivers, the wire's (readable) value is resolved by a function of the source
drivers and their strengths.
A subset of statements in the Verilog language are synthesizable. Verilog modules that
conform to a synthesizable coding style, known as RTL (register-transfer level), can be
physically realized by synthesis software. Synthesis software algorithmically transforms the
(abstract) Verilog source into a netlist, a logically equivalent description consisting only of
elementary logic primitives (AND, OR, NOT, flip-flops, etc.) that are available in a
specific FPGA or VLSI technology. Further manipulations to the netlist ultimately lead to a
circuit fabrication blueprint (such as a photo mask set for an ASIC or a bitstream file for
an FPGA).
 ELEVATOR CONTROL SYSTEM

An elevator is a device designed as a convenience appliance that has evolved to become an unavoidable
feature of modern day urban life. An elevator is defined as, A machine that carries people or goods up and
down to different levels in a building or mine. While a standalone elevator is a simple electro-mechanical
device, an elevator system may consist of multiple standalone elevator units whose operations are controlled
and coordinated by a master controller. Such controllers are designed to operate with maximum efficiency in
terms of service as well as resource utilization. This project details the design of an elevator controller using
VERILOG. The Elevators/Lifts are used in multi store buildings as a means of transport between various floors.
Elevator is a device designed as a convenience appliance that has evolved to become an unavoidable
features of modern day in urban life normally .The lifts is controlled by Microprocessor based systems, which are
costlier. It is proposed to design a low cost and compact dedicated controller. The Elevator Controller is a
device used to control a lift motion and to indicate the direction of motion, and the present floor level, etc. The
device control the lift motion by means of accepting the floor level as input and generate control signals (for
control the lift motion) as output. We developed a VERILOG code for 3-story elevator control system for the
cases of elevator moving up and down. The design and simulation of the Elevator controller can be performed
using VERILOG. Also the Timings of various signals can be verified.
VERILOG is a hardware description language used in electronic design automation to describe digital and
mixed-signal systems such as field- programmable gate arrays and integrated circuits. The key advantage of
VERILOG when used for systems design is that it allows the behaviour of the required system to be described
(modelled) and verified (simulated) before synthesis calculation block can be used in many other projects.
However, many formational and functional block parameters can be tuned that are capacity parameters,
memory size, element base, block composition and interconnection structure.
 ALGORITHM

At any floor when input button is pressed to reach any desired floor
the state will be changed.
According to this state the motor move the car upward or
downward.
As car reached at desired floor, limiter or sensor generate an input
to change the state.
At this state output 00 generated to the H-bridge which will stop
the car motor.
According to next instruction (input) the same procedure repeat.
BLOCK DIAGRAM
 Description of Elevator Control System

There are seven states for three level elevator control systems. To
control the elevator system on each floor, input request are
provided and push buttons are used for these requests.
Three states F1, F2, F3 represent the floors.
Two states MU2, MU3 represents the state for which motor rotates in
upward direction.
At MU2, MU3 states output HBRG=01 is generated which is
attached to H-bridge to control the direction of motor.
Two states MD1, MD2 represent the state for which motor rotates in
downward direction.
At MD1, MD2 states output HBRG=10 is generated which is
attached to H-bridge to control the direction of motor.
The transitions PB1, PB2, PB3 are inputs connected to Push buttons.
 Implementation

FPGA design work flow of elevator control system is shown in Fig . First logic function is
created as state diagram using Xilinx State CAD tool, HDL code generated from state diagram
which is used in Xilinx Project Navigator to analyse register transfer level (RTL) schematic as
shown in Fig. Finally, the generated binary file by Xilinx ISE 7.1 is downloaded in FPGA which now
behaves according to control algorithm written in State CAD.
As applied system for three floors, PB1, PB2, PB3 represent the input push buttons. S1, S2, S3
represents inputs
generated by sensors. Push buttons are used to give instruction for desired floor and sensor used
as input to stop elevator car at desired floor. HBRG and FLOOR is output vector, Output H-bridge
(HBRG) control the direction of motor rotation, FLOOR output is to shows the floor number
accordingly on seven segment display.
 Working Mechanism

At state F1, when PB1 is pressed, the state remains same using Else transition as
shown in Fig 2.

When PB2 is pressed the state changes into MU2 state and output HBRG=01 is
generated and motor starts to rotate upward. When sensor S2 is detected due to
transition S2 at that state, state will change to F2 state. Output HBRG=00 is
generated which stops the motor and one instruction is completed. At F1, When PB3
is
pressed the state changes into MU3, output HBRG=01 is generated and motor
starts to rotate upward. When sensor S3 is detected due to transition S3 at that state,
state will change to F3. Output HBRG=00 is generated which stops the motor
and one instruction is completed. At state F2, F3 the instructions for inputs PB1, PB2,
PB3 will executed in the same manner.

Fig. 2. Diagram for Floor 1 Diagram for Floor 2

 CONCLUSION

The FPGA based elevator control system provides more flexibility, compatible than
Microcontroller PLC based control system in which handwritten programming is
used. In this way embedded system engineer can design a control system after a lot
of process and errors that are comes in handwritten HDL programming. The
designed elevator control system is implemented using finite state machine
mechanism using Xilinx StateCAD tool that allows designer to change system
without text oriented and errors prone rules in a time saving manner. Simulations
have shown that this technique is quite promising.
Reconfiguration possibilities of FPGA based control system by software and high
speed due to parallel processing enhance productivity and reduce system
development cost.