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LOOSLEY Coupled

This document describes a loosely coupled multiprocessor configuration with the following key points: 1. It has multiple independent processor modules that communicate via a shared system bus and memory, without direct connections between modules. 2. Each module can access shared resources and its private subsystem concurrently, improving parallel processing performance. 3. The system can scale modularly and failures are isolated to single modules, improving reliability.

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Sivaprakasam Karthikeyan
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256 views10 pages

LOOSLEY Coupled

This document describes a loosely coupled multiprocessor configuration with the following key points: 1. It has multiple independent processor modules that communicate via a shared system bus and memory, without direct connections between modules. 2. Each module can access shared resources and its private subsystem concurrently, improving parallel processing performance. 3. The system can scale modularly and failures are isolated to single modules, improving reliability.

Uploaded by

Sivaprakasam Karthikeyan
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPT, PDF, TXT or read online on Scribd
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LOOSELY COUPLED

CONFIGURATION
Has shared system bus, system memory, and system I/O

Each processor has its own clock as well as its own memory.

Clocks are of similar frequency, but asynchronous towards each


other.

Used for medium to large multiprocessor systems

Each module is capable of being the bus master

Any module could be a processor capable of being a bus master, a


coprocessor configuration or a closely coupled configuration.
LOOSELY COUPLED
CONFIGURATION
No direct connections between the modules.
Each share the system bus and communicate
through shared resources.
Processor in their separate modules can
simultaneously access their private subsystems
through their local buses, and perform their
local data references and instruction fetches
independently.
This results in improved degree of concurrent
processing.
ADVANTAGES
High system throughput can be achieved by having
more than one CPU.
The system can be expanded in modular form. Each bus
master module is an independent unit and normally
resides on a separate PC board. One can be added or
removed without affecting the others in the system.
A failure in one module normally does not affect the
breakdown of the entire system and the faulty module
can be easily detected and replaced
Each bus master has its own local bus to access
dedicated memory or IO devices so a greater degree of
parallel processing can be achieved.
BUS CONTENTION(ARBITRATION)

Bus Arbitration (contention): Make sure that


only 1 processor can access the bus at any
given time.
Must synchronize local and system clocks for
synchronous transfer
Requires control chips to tie into the system
bus
Needs some kind of priority allocation
Daisy Chaining
Daisy Chaining

Need a bus controller to monitor bus busy and


bus request signals
Sends a bus grant to a Master >> each Master
either keeps the service or passes it on
Controller synchronizes the clocks
Master releases the Bus Busy signal when
finished.
Polling
Polling

Controller sends address of device to grant


bus access
Can use priority resolution here:
memory= highest priority
Highest priority is granted first, if it does not
respond, then a lower priority is granted, and
so on until someone accepts
(ie: one request line, 3-bit grant line)
Independent request
Independent request
Each master has a request and grant line

Now just a question of priority

Could have fixed priority, rotating priority, etc.

usually fixed because memory is desired to be the highest


priority

Synchronization of the clocks must be performed once a


Master is recognized

Master will receive a common clock from one side and pass it
to the controller which will derive a clock for transfer

Can accurately predict calculations (since memory is always


the highest priority)

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