Introduction to Computer Engineering

Lecture 10: Building Blocks for Combinational

Logic (1) Timing Diagram, Mux/DeMux
 N Combinational M
inputs circuits outputs

 Outputs, “at any time”, are determined by the input combination

 When input changed, output changed immediately
 Real circuits is imperfect and have “propagation delay”
 A combinational circuit
 Performs logic operations that can be specified by a set of
Boolean expressions
 Can be built hierarchically

2
 Describe the functionality of a logic circuit
across time
 Represented by a waveform
 For combinational logic, Output is a function
of inputs

3
 t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 Time

Output
(No Delay)

Note that the Output change can occur “at any Time” for
Combinational logic 4
 A Y
X F

B
Z

t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10

F
 A Y
X F

B
Z

t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10

A B F
0 1 1
1 1 0 F = A B
0 0 0
F 1 0 1
 N Combinational M
inputs circuits outputs

 Outputs, “at any time”, are determined by the input combination

 We will discuss
 Multiplexers / De-Multiplexers
 Decoders / Encoders
 Comparators
 Parity Checkers / Generators
 Binary Adders / Subtractors
 Integer Multipliers
  Functionality: Selection
of a particular input
 Route 1 of N inputs (A)
En
A0 to the output F
A1  Require
4-to-1
F log 2Nselection
A2 Mux bits (S)
 En(able) bit can disable
A3
S1 S0 the route and set F to 0
 S1 S0 A3 A2 A1 A0 F
0 0 X X X 0 0
A0
0 1 X X 0 X 0
A1 F 1 0 X 0 X X 0
4-to-1
A2 Mux 1 1 0 X X X 0
0 0 X X X 1 1
A3
S1 S0 0 1 X X 1 X 1
1 0 X 1 X X 1
1 1 1 X X X 1

9
 S1 S0 F
A0
0 0 A0
A1 F
4-to-1 0 1 A1
A2 Mux 1 0 A2

A3 1 1 A3
S1 S0

F  S1S0A0  S1S0A1  S1S0A2  S1S0A3

10
S1
F  S1S0A0  S1S0A1  S1S0A2  S1S0A3
S0
F
A0

A1

A2

A3

11
 En En S1 S0 F
A0
0 X X 0
A1 F
4-to-1 1 0 0 A0
A2 Mux 1 0 1 A1

A3 1 1 0 A2
S1 S0
1 1 1 A3

F  En  (S1S0A0  S1S0A1  S1S0A2  S1S0A3)

 EnS1S0A0  EnS1S0A1  EnS1S0A2  EnS1S0A3

12
 F  En  (S1S0A0  S1S0A1  S1S0A2  S1S0A3)
S1

S0 F

A0

A1

A2

A3

En
13
 F  EnS1S0A0  EnS1S0A1  EnS1S0A2  EnS1S0A3
S1

S0
F
A0

A1
Reduce one Gate Delay
by using 4-input
A2
AND gate for the 2nd
level
A3

En
14
S1
S0

A0 S1 S0 F
0 0 A0

A1 0 1 A1
F 1 0 A2
1 1 A3
A2

A3
 S1
S0=0

A0 S1 S0 F
0 0 A0

A1 0 1 A1
F 1 0 A2
1 1 A3
A2

A3

16
S1=0
S0=0

A0 S1 S0 F
A0 0 0 A0

A1 0 1 A1
F 1 0 A2
1 1 A3
A2
A2

A3

17
 S1
S0=1

A0 S1 S0 F
0 0 A0

A1 0 1 A1
F 1 0 A2
1 1 A3
A2

A3

18
S1=1
S0=1

A0 S1 S0 F
A1
0 0 A0

A1 0 1 A1
F 1 0 A2
1 1 A3
A2
A3

A3

19
 En
S1=1
S0=1

A0

En S1 S0 F
A1
0 X X 0

1 0 0 A0
A2
1 0 1 A1

F 1 1 0 A2
A3
1 1 1 A3
 A0
X En S1 S0 F
Y
0 X X Z
A1
1 0 0 A0

En=1 X=S0 Y=S0 1 0 1 A1

En=0 X=0 Y=1 (To disable both TG)
1 1 0 A2

X=En· S0 1 1 1 A3
Y=En + En·S0 = En + S0

21
 X=En· S0

S0 Y=En + En·S0 = En + S0

En A0
X En S1 S0 F
Y
0 X X Z
A1
1 0 0 A0

1 0 1 A1

1 1 0 A2

1 1 1 A3
 X=En· S0

S0 Y=En + En·S0 = En + S0

A0
En
En S1 S0 F

0 X X Z
A1
1 0 0 A0

1 0 1 A1
A2
1 1 0 A2

1 1 1 A3

A3
 S1
S0

A0
En
F

A1
En S1 S0 F

A2 0 X X Z
1 0 0 A
0
1 0 1 A
A3 1
1 1 0 A
2
En X=En· S0
S1
Y=En + En·S0 = En + S0
S0

A0
X F
Y
A1

En S1 S0 F
0 X X Z
A2
1 0 0 A
0

Only 1 0 1 A
A3
Disable the 1
2nd level 1 1 0 A
2
 En
A[3:0]
A3..0 2-to-1
F[3:0]
Mux En SEL F[3:0]
(4-bit bus) 0 X 0000
B3..0
B[3:0] 1 0 A[3:0]
SEL
1 1 B[3:0]

26
A0
F0
A1
F1
Fx=Ax·En·SEL+Bx·En·SEL
A2
F2
A3
F3 En SE F[3:0]
L
SEL 0 X 0000
B0 1 0 A[3:0]

B1 1 1 B[3:0]

B2

B3

En
F(A, B, C)  A BC  ABC  ABC  ABC

Each input in a MUX is a minterm

F(A, B, C)   m(1, 2, 6, 7)

0
A0
1 A1
1 A2 8-to-1 F
0 A3 Mux
0 A4
0 A5
1 A6
1 A7
S2 S1 S0

A B C 28
F(A, B, C)   m(1, 2, 6, 7)

F  A BC  ABC  ABC  ABC

A B F
0 0
0 1
1 0
1 1
 F   m(1, 2, 6, 7)
F  A BC  ABC  ABC  ABC

A B F
C En
A0 0 0 C
C A1 F 0 1 C
4-to-1
0 A2 Mux
1 0 0
1 A3
Vdd
S1 S0 1 1 1

A B
F   m(1, 2, 6, 7)
F  A BC  ABC  ABC  ABC

B C F
0 0
0 1
1 0
1 1
 F   m(1, 2, 6, 7)
F  A BC  ABC  ABC  ABC

B C F
En
A0 0 0 0
A A1 F
Vdd 4-to-1 0 1 A
A2 Mux
1 0 1
A A3
S1 S0 1 1 A

B C
A0 D0

A1 F D1
4-to-1 A 1-to-4
A2 Mux DeMux D2
A3 D3
S1 S0 S1 S0

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 S1 S0 D3 D2 D1 D0
0 0 0 0 0 A
0 1 0 0 A 0
D0
1 0 0 A 0 0
D1 1 1 A 0 0 0
A 1-to-4
DeMux D2
D3 D 0  S1 S0 A
S1 S0
D1  S1S0 A
D 2  S1 S0 A
D 3  S1S0 A
 S1 S0 D3 D2 D1 D0
S1 0 0 0 0 0 A
D0 0 1 0 0 A 0
S0
1 0 0 A 0 0
D1 1 1 A 0 0 0

D2 D 0  S1 S0 A
D1  S1S0 A
D3
D 2  S1 S0 A
D 3  S1S0 A
A
S1

D0
S0

En S1 S0 D3 D2 D1 D0
D1
0 X X 0 0 0 0

1 0 0 0 0 0 A
D2
1 0 1 0 0 A 0

1 1 0 0 A 0 0
D3
1 1 1 A 0 0 0

En A
36