Microprocessor System Design

AVR Microcontroller

Omid Fatemi

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 Contents

Introduction

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 Introduction
General-purpose microprocessor

CPU for Computers

No RAM, ROM, I/O on CPU chip itself
Example Intels x86, Motorolas 680x0
Many chips on mothers board
Data Bus
CPU
General-
Serial
Purpose RAM ROM I/O Timer COM
Micro- Port
Port
processor
Address Bus

General-Purpose Microprocessor System

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 Microcontroller

A smaller computer
On-chip RAM, ROM, I/O ports...
Example AVR, Intels 8051, Zilogs Z8 and PIC
16X

CPU RAM ROM

A single chip
Serial
I/O Timer COM
Port
Port
Microcontroller

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 Microprocessor vs.
Microcontroller

Microprocessor Microcontroller
CPU is stand-alone, CPU, RAM, ROM, I/O
RAM, ROM, I/O, timer are and timer are all on a
separate
single chip
designer can decide on
the amount of ROM, fix amount of on-chip
RAM and I/O ports. ROM, RAM, I/O ports
More consumption for applications in which
power cost, power and space are
More computing power critical
versatility Less applications
general-purpose

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 Embedded System

Embedded system means the processor is

embedded into that application.
An embedded product uses a microprocessor
or microcontroller to do one task only.
In an embedded system, there is only one
application software that is typically burned
into ROM.
Example printer, keyboard, video game
player

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 Three Criteria in Choosing a
Microcontroller

meeting the computing needs of the task

efficiently and cost effectively
speed, the amount of ROM and RAM, the number of I/O
ports and timers, size, packaging, power consumption
easy to upgrade
cost per unit
availability of software development tools
assemblers, debuggers, C compilers, in circuit emulator,
simulator, technical support
wide availability and reliable sources for the
microcontroller.

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Most common microcontrollers

8-bit microcontrollers
AVR
PIC
HCS12
8051
32-bit microcontrollers
ARM
PIC32

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 AVR internal architecture

40 PIN DIP
(XCK/T0) PB0 1 40 PA0 (ADC0)
(T1) PB1 2 RAM 39 EEPROM
PA1 (ADC1) Timers
(INT2/AIN0) PB2 3 38 PA2 (ADC2)

PROGRAM
(OC0/AIN1) PB3 4 MEGA32 37 PA3 (ADC3)
(SS) PB4 5 36 PA4 (ADC4)
ROM (MOSI) PB5 6 35 PA5 (ADC5)
(MISO) PB6 7 34 PA6 (ADC6)
Program (SCK) PB7 8 33 PA7 (ADC7)
RESET 9 32 AREF
Bus Bus
VCC 10 31 AGND
CPU GND 11 30 AVCC
XTAL2 12 29 PC7 (TOSC2)
XTAL1 13 28 PC6 (TOSC1)
(RXD) PD0 14 27 PC5 (TDI)
(TXD) PD1 15 26 PC4 (TDO)
(INT0) PD2 16 25 PC3 (TMS)
(INT1) PD3 17 24 PC2 (TCK)
(OC1B) PD4 18
Interrupt 23 PC1 (SDA) Other
OSC (OC1A) PD5 19 22 Ports
PC0 (SCL)
(ICP) PD6 20 Unit 21 PD7 (OC2) Peripherals

I/O
PINS

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 AVR different groups

Classic AVR
e.g. AT90S2313, AT90S4433
Mega
e.g. ATmega8, ATmega32, ATmega128
Tiny
e.g. ATtiny13, ATtiny25
Special Purpose AVR
e.g. AT90PWM216,AT90USB1287

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 Lets get familiar with the AVR
part numbers
ATmega128

Atmel group
Flash =128K

ATtiny44 AT90S4433

Atmel
Tiny Flash =4K Atmel Classic
Flash =4K
group group

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 Introduction to Assembly
Chapter 2

The AVR microcontroller

and embedded
systems
using assembly and c

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 Topics
AVRs CPU
Its architecture
Some simple programs
Data Memory access
Program memory
RISC architecture
RAM EEPROM Timers

PROGRAM
Flash ROM

Program Data
Bus Bus
CPU

Interrupt Other
OSC Ports
Unit Peripherals

I/O
PINS

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 AVRs CPU
AVRs CPU
ALU
32 General Purpose registers
(R0 to R31)
PC register R0
Instruction decoder ALU R1
R2

SREG: I T H S V N Z C
R15

CPU R16
R17

PC

R30
Instruction decoder
R31
Instruction Register
registers

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 Some simple instructions
1. Loading values into the general purpose
registers
LDI (Load Immediate)
LDI Rd, k
Its equivalent in high level languages:
Rd = k
Example:
LDI R16,53
R0
R16 = 53 R1
ALU
LDI R19,132 R2

LDI R23,0x27 SREG: I T H S V N Z C
R23 = 0x27 R15

CPU R16
R17

PC
R30
Instruction decoder
R31
Instruction Register
registers
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 Some simple instructions
2. Arithmetic calculation
There are some instructions for doing Arithmetic and
logic operations; such as:
ADD, SUB, MUL, AND, etc.
ADD Rd,Rs
Rd = Rd + Rs
Example:
ADD R25, R9 R0
ALU R1
R25 = R25 + R9 R2
ADD R17,R30

SREG: I T H S V N Z C
R17 = R17 + R30 R15

CPU R16
R17

PC
R30
Instruction decoder
R31
Instruction Register
registers
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 A simple program
Write a program that calculates 19 + 95
LDI R16, 19 ;R16 = 19
LDI R20, 95 ;R20 = 95
ADD R16, R20 ;R16 = R16 + R20

R0
ALU R1
R2

SREG: I T H S V N Z C
R15

CPU R16
R17

PC
R30
Instruction decoder
R31
Instruction Register
registers
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 A simple program
Write a program that calculates 19 + 95 + 5
LDI R16, 19 ;R16 = 19
LDI R20, 95 ;R20 = 95
LDI R21, 5 ;R21 = 5
ADD R16, R20 ;R16 = R16 + R20
ADD R16, R21 ;R16 = R16 + R21

LDI R16, 19 ;R16 = 19

LDI R20, 95 ;R20 = 95
ADD R16, R20 ;R16 = R16 + R20
LDI R20, 5 ;R20 = 5
ADD R16, R20 ;R16 = R16 + R20

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 Some simple instructions
2. Arithmetic calculation
SUB Rd,Rs
Rd = Rd - Rs
Example:
SUB R25, R9
R25 = R25 - R9
SUB R17,R30
R17 = R17 - R30 R0
ALU R1
R2

SREG: I T H S V N Z C
R15

CPU R16
R17

PC
R30
Instruction decoder
R31
Instruction Register
registers
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 Some simple instructions
2. Arithmetic calculation
INC Rd
Rd = Rd + 1
Example:
INC R25
R25 = R25 + 1

R0
DEC Rd ALU R1
Rd = Rd - 1 R2

Example: SREG: I T H S V N Z C
R15
DEC R23
R23 = R23 - 1 CPU R16
R17

PC
R30
Instruction decoder
R31
Instruction Register
registers
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 Address Name Address Name Address Name
I/O
$00
$01
Mem.
$20
$21
TWBR
TWSR
Data Address Space
I/O
$16
$17
Mem.
$36
$37
PINB
DDRB
I/O
$2B
$2C
Mem.
$4B
$4C
OCR1AH
TCNT1L
$02 $22 TWAR $18 $38 PORTB $2D $4D TCNT1H
$03 $23 TWDR $19 $39 PINA $2E $4E TCCR1B
$04 $24 ADCL $1A $3A DDRA $2F $4F TCCR1A
$05 $25 ADCH $1B $3B PORTA $30 $50 SFIOR
$06 $26 ADCSRA $1C $3C EECR OCDR
$07 $27 ADMUX $1D $3D EEDR $31 $51 General RAM EEPROM Timers
OSCCAL
$08 $28 ACSR $1E $3E EEARL $32 $52 Purpose
TCNT0
$09 $29 UBRRL $1F $3F PROGRAM
EEARH $33 $53 Registers
TCCR0
$0A $2A UCSRB UBRRCROM $34 $54 MCUCSR
$20 $40
$0B $2B UCSRA UBRRH $35 $55 MCUCR
Program CPU
$0C $2C UDR $21 $41 WDTCR $36 $56 TWCRData
$0D $2D SPCR $22 $42 ASSR Bus
$37 $57 SPMCRBus address bus
$0E $2E SPSR $23 $43 OCR2 $38 $58 TIFR data bus
control bus
$0F $2F SPDR $24 $44 TCNT2 $39 $59 TIMSK Data
$10 $30 PIND $25 $45 TCCR2 $3A $5A GIFR
$11 $31 DDRD 8 bit
$26 $46 ICR1L $3B $5B GICR
Bus
Data Address
$12 $32 PORTD $27R0 $47 ICR1H $3C $5C OCR0
Space
$13 $33 PINC $28R1 $48 OCR1BL $3D $5D SPL
$14
$0000 $34 DDRC $29R2 $49 OCR1BH $3E $5E SPH Interrupt Other
$0001 $35
$15 General
PORTC OSC Ports
$2A $4A OCR1AL $3E $5E SREG Unit Peripherals
...

Purpose
...

Registers R31
$001F I/O Address I/O
$0020 Example:
TWBR
TWSR
$00 Add contents
$01
of location
Example: 0x90
Store to contents
0x53 into PINS of location
the SPH 0x95
register.
Standard I/O Example:
and store What doesinthe
the result following
location
The
LDS
STS (Load
(Store instruction
0x313.
address of SPH
direct do?space)
isdata
from
direct to 0x5E
data space)
Example: Write a program that stores 55 into location 0x80 of RAM.
...
...

Registers Example: Write a program that copies the contents of location 0x80
$005F LDS
SPH
of RAM
SREG
$3E
R20,2
Solution:
into location 0x81.
$3F
$0060 LDS
STS Rd, addr ;[addr]=Rd
addr,Rd ;Rd = [addr]
General LDS R20, 0x90 Solution: ;R20 = [0x90]
purpose Solution:
Answer:
...

RAM
LDS R20,
LDI R21, 55
0x95 LDI =;R21
Example:
;R20 R20,= 0x53
55 [0x95] ;R20 = 0x53
(SRAM) Solution:
It copies
ADD the contents
R20, R21 of
STSR2 ;R20
into R20;
0x5E,= R20
R20as+ 2R21
is the;SPH
address
= R20of R2.
STS 0x80, R20
LDS R20, 0x80 LDS;[0x80]
STS R1, =
;R20 R20
0x60
0x60,R15 = 55
= [0x80]
; [0x60] = R15
STS 0x313, R20 ;[0x313] = R20
STS 0x81, R20 ;[0x81] = R20 = [0x80]
$FFFF
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 Data Address Space
General RAM EEPROM Timers
Purpose
PROGRAM
Registers
ROM

Program CPU Data

Bus Bus address bus
data bus
control bus
Data
8 bit Bus
Data Address
R0
Space
Example:
R1
R2
Write a program that adds the contents of the PINC IO
$0000 Other
$0001 General register to the contents of
OSCPIND andInterrupt
stores the result
Unit
Ports in location 0x90
Peripherals
...

Purpose of the SRAM OUT

IN (IN(OUT toIO
from IOlocation)
location)
...

Registers R31
$001F I/O Address I/O
$0020 TWBR
Solution:
$00
OUT IOAddr,Rd
PINS
;[addr]=Rd
Standard I/O
TWSR $01
IN Rd,IOaddress
Using Names of;Rd
IO = [addr]
registers
...
...

Registers
SPH $3E
IN R20,PINC ;R20 = PINC
$005F SREG $3F
$0060
IN R21,PIND Example:
;R21 = PIND
General Example:
purpose
...

RAM ADD R20,R21 ;R20 SPH,R12

OUT = R20 + R21;OUT 0x3E,R12
(SRAM) OUT
IN R1,0x3F,R12
0x3F ;R1 ;SREG = R12
= SREG
STS 0x90,R20 ;[0x90]
IN = R20
R15,SREG ;IN R15,0x3F
OUT 0x3E,R15;R17
IN R17,0x3E ;SPH = R15
= SPH
$FFFF
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 Status Register (SREG)
SREG: I T H S V N Z C
Carry
Interrupt oVerflow Zero
Temporary Negative
Sign
Data Address
Half carry N+V Space
Example:Show
Example:
Example:
Example: Showthe
Show
Show thestatus
the
the status of
status
status ofthe
of
of theC,
the
the C,H,
C,
C, H,$0000
H,
H, andZZ
and
and
and ZZflags
flagsafter
flags
flags afterthe
after
after theaddition
the
the addition
$0001 General
subtraction
subtraction
of
of 0x9C of
of 0x9C
0x23
0x73 from
from
from 0x9C
0xA5
0x52 in
in the
the following
following
0x64 in the following instructions:
0x38 and 0x2F instructions:
instructions:
Purpose

...
LDI LDILDI 0x38
LDI
R16, R20, 0x9C
R20,
R20, 0x9C
0xA5
0x52;R16 = 0x38 Registers
R0 $001F IO Address
ALU LDI LDI 0x2F
LDI
LDI
R17, R21,
R21,
R21, 0x9C
0x23
0x73
R1 0x64
;R17 = $0020
0x2F TWBR $00
TWSR $01
R2 Standard IO
ADD SUB R17R20,
SUB
ADD
R16, R20, R21
R20, R21;add R17;add
R21 ;subtract
;subtract
R21 toR21
to Registers
R16 R21 from R20
R20from R20

...
...

SPH $3E
SREG: I T H S V N Z C
Solution:
Solution:
Solution: R15 11
$005F SREG $3F
Solution:
CPU $52
$9C
$A5
$38
$9C
- $23
$73
0101
R16
0011
1001
0111
0010
1001 1100
1010 1100
0101
1000
R17 0011
$0060
General
purpose
...
+-- +$64
$9C
$2F 10010100
0010
0110 1100
0011
1111 RAM
$DF 1101 1111 R20 = $DF

PC $00
$82
$67 0000
1000
0110 0000
0010
0111 R20
R20
R16 = $00
= 00
$82
0x67
$100 1 0000 0000 R20 =
(SRAM)
C = 1 because R21 is bigger than R20 and there is a borrow from D8 bit.
CC===100because
C becausethere
because R21 is
R21 is not
isnot bigger
bigger
a carry
R30 than R20
than
beyond R20 andbit.
and
the D7 there is
there is no
no borrow
borrow from
from D8
D8 bit.
bit.
Z
C == 00 decoder
because
because the
thereR20
is has
no a value
carry otherthe
beyond than
D7zero after the subtraction.
Instruction
ZZ =
H == 1
01 because
because there
because the R20
the R20 iscarry
is ahaszero after
a value
from the D3
other
the than 0 bit.
subtraction.
to theafter the subtraction.
D4 bit.
H = 1 because there isR31 a borrow
carry from
from D4D3
the toto
D3.
the D4 bit.
ZH
H =
= 00 because
because there
there is
is no
no borrow
borrow from
from D4
D4 to
to D3.
D3.
Z = 0 because the R16 (the result) has a value 0other
= 1 because
Instruction Register the R20 (the
registers
result) has a value in it after
than 0 the addition.
after the addition.
$FFFF
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 Assembler Directives
.EQU and .SET

.EQU name = value

Example:
.EQU COUNT = 0x25
LDI R21, COUNT ;R21 = 0x25
LDI R22, COUNT + 3 ;R22 = 0x28

.SET name = value

Example:
.SET COUNT = 0x25
LDI R21, COUNT ;R21 = 0x25
LDI R22, COUNT + 3 ;R22 = 0x28
.SET COUNT = 0x19
LDI R21, COUNT ;R21 = 0x19

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 Assembler Directives
.INCLUDE

.INCLUDE filename.ext
M32def.inc
.equ SREG = 0x3f
.equ SPL = 0x3d
.equ SPH = 0x3e
....
.equ INT_VECTORS_SIZE = 42 ; size in words

Program.asm
.INCLUDE M32DEF.INC
LDI R20, 10
OUT SPL, R20

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 Assembler Directives
.ORG
.ORG address

00 E205
01 0000
Program.asm 02 0000

.ORG 0 03 0000

LDI R16, 0x25 04 0000

.ORG 0x7
assembler 05 0000
LDI R17, 0x34 06 0000
LDI R18, 0x31 07 E314
08 E321
09 0000
0A 0000

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 Assembler
Assembly

EDITOR
PROGRAM assembler
myfile.asm

ASSEMBLER
PROGRAM Machine
Language

myfile.eep myfile.hex myfile.map myfile.lst myfile.obj

DOWNLOAD TO DOWNLOAD TO
AVRs EEPROM AVR s FLASH

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 Flash memory and PC register
00 E205
E205
LDI R16, 0x25 01 E314
LDI R17, $34 02 E321
LDI R18, 0x31
03 0F01
ADD R16, R17
ADD R16, R18 04 0F02
LDI R17, 11 0516-bit
E01B
ADD R16, R17
06 0F01
STS SUM, R16
HERE:JMP HERE 07 9300
9300
08 0300
0300 RAM EEPROM Timers
09 940C
940C
PROGRAM
0A
Flash0009
0009
ROM ALU

16bit
PC: 3
0
9
1
5
2
A
7
4
8
B
6 Data
16bit CPU Bus
Instruction dec.
Program
Bus

Interrupt Other
OSC Ports
Unit Peripherals

I/O
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 Fetch and execute
Old Architectures 00 E205
01 E314
02 E321
Instruct 4
03 0F01
Instruct 3
04 0F02
Instruct 2
0516-bit
E01B
Instruct 1
06 0F01
07 9300
08 0300 RAM EEPROM Timers
Fetch
09 940C
PROGRAM
0A
Flash0009
ROM ALU

PC: Data
CPU Bus
Execute
Instruction dec.
Program
Bus

Interrupt Other
OSC Ports
Unit Peripherals

I/O
PINS
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 Pipelining
Pipelining 00 E205
01 E314
02 E321
Instruct 4 03 0F01
Instruct 3 04 0F02
Instruct 2 0516-bit
E01B
Instruct 1 06 0F01
07 9300
08 0300 RAM EEPROM Timers
Fetch 09 940C
PROGRAM
0A
Flash0009
ROM ALU

PC: Data
CPU Bus
Execute Program Instruction dec.

Bus

Interrupt Other
OSC Ports
Unit Peripherals

I/O
PINS
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 How to speed up the CPU

Increase the clock frequency

More frequency More power consumption & more heat
Limitations
Change the architecture
Pipelining
RISC

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 Changing the architecture
RISC vs. CISC

CISC (Complex Instruction Set Computer)

Put as many instruction as you can into the CPU
RISC (Reduced Instruction Set Computer)
Reduce the number of instructions, and use your
facilities in a more proper way.

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 RISC architecture

Feature 1
RISC processors have a fixed instruction size. It makes
the task of instruction decoder easier.
In AVR the instructions are 2 or 4 bytes.
In CISC processors instructions have different lengths
E.g. in 8051
CLR C ; a 1-byte instruction
ADD A, #20H ; a 2-byte instruction
LJMP HERE ; a 3-byte instruction

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 RISC architecture

Feature 2: reduce the number of instructions

Pros: Reduces the number of used transistors
Cons:
Can make the assembly programming more difficult
Can lead to using more memory

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 RISC architecture

Feature 3: limit the addressing mode

Advantage
hardwiring
Disadvantage
Can make the assembly programming more difficult

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 RISC architecture
Feature 4: Load/Store
LDS R20, 0x200
LDS R21, 0x220
ADD R20, R21
STS 0x230, R20

RAM EEPROM Timers

PROGRAM
Flash ROM ALU

PC: Data
CPU Bus
Instruction dec.
Program
Bus

Interrupt Other
OSC Ports
Unit Peripherals

I/O
PINS

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 RISC architecture
LDS R20, 0x100 ; R20 = [0x100]
ADD R20, R21
ADD R20,R21 ; R20 = R20 + R21
LDS R20, 0x100

Feature 5 (Harvard architecture): separate

buses for opcodes and operandsFetch
Advantage: opcodes and operands can go in and
out of the CPU together.
Disadvantage: leads to more cost in general
purpose computers. Execute

Control bus Control bus

Code Data
Memory Data bus CPU Data bus Memory
Address bus Address bus

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 RISC architecture

Feature 6: more than 95% of instructions are

executed in 1 machine cycle

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 RISC architecture

Feature 7
RISC processors have at least 32 registers. Decreases
the need for stack and memory usages.
In AVR there are 32 general purpose registers (R0 to
R31)

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