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Clock Buffer Polarity Assignment For Power Noise Reduction

This document discusses three algorithms to reduce power noise in clock networks by assigning different polarities to clock buffers. The first algorithm uses partitioning to assign polarities. The second uses 2-coloring on a minimum spanning tree. The third uses recursive minimum matching. The objectives are to reduce peak current by 50% and average delay variations by 51%. The algorithms will be implemented using C and Spice simulations to test the expected outcomes of reduced power noise.

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66 views16 pages

Clock Buffer Polarity Assignment For Power Noise Reduction

This document discusses three algorithms to reduce power noise in clock networks by assigning different polarities to clock buffers. The first algorithm uses partitioning to assign polarities. The second uses 2-coloring on a minimum spanning tree. The third uses recursive minimum matching. The objectives are to reduce peak current by 50% and average delay variations by 51%. The algorithms will be implemented using C and Spice simulations to test the expected outcomes of reduced power noise.

Uploaded by

rockfloyd
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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Clock Buffer Polarity Assignment for

Power Noise Reduction

Name: Sathya Kanth V.


1580910063
Guided by:
Mr.B.Srinath AP(O.G)
OVERVIEW
OBJECTIVE.
BACKGROUND.
STATEMENT OF WORK.
MODE OF IMPLETMENTATION.
EXPECTED OUTCOMES.
SHEDULE FOR PHASE ONE

05/08/10
INTRODUCTION
When Supply voltage decreases with scaling, circuit performance becomes
increasingly vulnerable to power/ground noise.
 A main culprit of power noise is clock network
 Different signal polarities on clock buffers are used.

05/08/10
OBJECTIVE

Power /ground noise is a major source of VLSI circuit timing


variations

To reduce clock network induced power noise by proposing three


algorithms

To reduce peak current and average delay variations by 50% and 51%
respectively

05/08/10
POWER DELAY CHANGE IN THE
PRESENCE OF POWER AND GROUND
NOISE

Advantages:
1) We study the effects of differential and common mode power/ground
noise on buffer delay.
2) can be incorporated into any existing gate delay calculation techniques
3) repeater chains, using buffers tend to have superior level induced delay
characteristics

Disadvantage:
1) Despite reduction of noise from lower-inductance packing, the relative
magnitude of delay change is still there

05/08/10
CLOCK SKEW
OPTIMIZATION FOR PEAK CURRENT
REDUCTION

ADVANTAGES
Current peaks caused by the simultaneous switching of highly loaded

clock lines and by the signal propagation's amplitude is reduced.


Peak current increased without any increase in power consumption.

DISADVANTAGES
Flip flops grouped into buckets that are switched at different times but

flip flops within same bucket switch on simultaneously

05/08/10
CLOCK SKEW OPTMISATION FOR
GROUND BOUNCE CONTROL
lADVANTAGES
 Reduces transient current drawn from the supply pins.
 Order of magnitude improvements in ground bounce are obtained.
 Reduction in package costs.
lDISADVANTAGES
 Effectiveness of this approach depends on available slack in the application.
 The effect of on chip decoupling capacitor is not considered.

05/08/10
IMPACT OF DELAY
VARIATION
Power/ground noise directly affects gate/buffer delay variation.
We define power noise and ground noise

The differential mode noise and common mode noise are evaluated
using

05/08/10
POLARITY ASSIGNMENT ALGORITHMS

We make use of three existing algorithms to solve our polarity assignment


problem

1. Partitioning

2. 2-colouring on min matching spanning tree

3. Recursive min matching

05/08/10
BUFFER TYPE SELECTION

We choose either inverting or non inverting type for each clock buffer after
polarity assignment

1) Buffer type matching: Performed for a pair of sequentially


adjacent flip flops at a time

2) Clock skew tuning : To run after buffer type matching to


restore original clock skew
MODE OF IMPLEMENTATION

lThe proposed procedures will be implemented using the help of


 C
 Spice

05/08/10
STATEMENT OF WORK

TEREATURE ABOUT THE PROJECTDESIGNING THE SYSTEM MODEL ANALYTICAL PART OF FDE TECHN
GETTING

SIMULATION OF FDE
TECHINQUES

05/08/10
EXPECTED OUTCOMES

The reduction of the peak current is expected to be by 50%.


The reduction in average delay variations is expected to be upto


a maximum of 51%.

05/08/10
SHEDULE FOR PHASE ONE

REVIEW 1
Design of OFDM System Model (Transmitter & Receiver) Using
MATLAB.
REVIEW 2
Getting Analytical part of ZF and MMSE

05/08/10
REFERENCES

L. H. Chen, M. Marek-Sadowska, and F. Brewer, “Buffer delay change in the


presence of power and ground noise,” IEEE Trans. Very LargeScale Integr.
(VLSI) Syst., vol. 11, no. 3, pp. 461–473, Jun. 2003.
L. Benini, P. Vuillod, A. Bogliolo, and G. De Micheli, “Clock
skewoptimization for peak current reduction,” J. VLSI Signal Process.,
vol.l16, no. 2/3, pp. 117–130, Jun./Jul. 1997.
A. Vittal, H. Ha, F. Brewer, and M. Marek-Sadowska, “Clock skew
optimization for ground bounce control,” in Proc. IEEE/ACMInt. Conf.
Comput.-Aided Des., Nov. 1996, pp. 395–399.

05/08/10
THANK YOU

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