The HCS12/MC9S12 Microcontroller

Chapter 1: Introduction to HCS12/MC9S12

The HCS12 Microcontroller

Han-Way Huang

Minnesota State University, Mankato

September 2009

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Number System Issue

• Computer hardware uses binary numbers to perform all operations.
• To display numbers produced by the computer, both the octal and hexadecimal
numbers have been used to shorten the representation.
• Human beings are used to decimal number system. Conversion is often needed
to convert numbers between the internal (binary) and external (decimal)
representations.
• It is common for mixed use of different number bases.
• A prefix is used to indicate the base of a number.

Table 1.1 Prefixes for number bases

Base Prefix Example
Binary % %10001010
Octal @ @123467
Decimal 12345678
Hexadecimal $ $392
(shorthand hex)

Modulus Math
• Computers perform modulus math because it uses a limited number of bits
(e.g., 8, 16, or 32 bits) to represent numbers.

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What is a computer?
Software
Hardware

Computer Hardware Organization

Processor

Common Bus (address, data, & control)

Control Unit

Datapath

Arithmetic
Logic Unit Memory
Output Input
Program Data
Units Units
Registers Storage Storage

Figure 1.1 Computer Organization

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The Processor
• A processor consists of arithmetic logic unit (ALU), control unit, and
registers.
• The ALU can perform many different operations.
• An ALU that can perform 4 operations is shown in Figure 1.1.
A B
n n
OpCode
CIN 1 0pcode
inverters
2 00 = ADD
0 1 Compa ra tor 01 = SUB
MUX2 (=?) 01 10 = AND
11 = OR
0 1
MUX1 ci n SUM

Adder
00
Y
Ca rry
X Cout
01

MUX3
n
n Result
AND 10

OR
n 11

Figure 1.1An ALU that implements ADD, SUB, AND, and OR opera tions

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Control Unit
• The control unit decodes machine codes and performs the operations specified
by the machine code.
• A machine instruction has several fields. A mandated field is the opcode field.
• Instruction execution is timed by a clock signal.
• The frequency of the clock signal used in an 8-bit or 16-bit microcontroller is from
a few mega hertz to several hundred mega Hertz
• The control unit uses a program counter to keep track of the address of the
instruction to be executed next.
• The fetched instruction is placed in the instruction register when is decoded,
and executed.
• Program instructions are normally stored in sequential locations in memory.
• The processor may not execute instructions in sequential due to the need to
execute instructions based on the condition or the need to repeat a certain group
of instructions.
• The processor uses conditional and unconditional branch (or jump)
instructions to change the program flow.

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Registers
• A register is a storage location inside the CPU.
• A register is used to hold data or address during the execution of an instruction.
• A register, very close to the ALU, provides fast access to operands for program execution.
• Some processors provide a dedicated register (often called an accumulator) as one of the
operands of most of the instructions.
• Freescale HCS12, Microchip PIC18, Intel 8051 microcontrollers use this approach.
• Other processors provide many general-purpose registers in the CPU that can be used
as operands of instructions.
• Atmel AVR and AVR32, Microchip PIC24 and PIC32, Freescale Coldfire use this approach.

Microprocessor
• A processor implemented in a single integrated circuit (IC).
• The first microprocessor, Intel 4004, was introduced in 1968.
• The Intel 8008, the first 8-bit microprocessor from Intel, was introduced in 1972.
• A microprocessor requires peripheral ICs to interface with I/O devices.
• A microprocessor does not have peripheral functions such as timers, A/D converters,
D/A converters, parallel I/O ports, and memory.
• The designer need to add peripheral ICs and memory devices to the microprocessor
in order to build a product.

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Microcontroller
• A microcontroller incorporates the processor and one or more of the following
peripheral functions and memory in one very large scale integrated circuit (VLSI):
1. Memory
2. Timer functions
3. Serial communication interface such as UART, I2C, SPI, CAN, and Ethernet
4. A/D converter
5. D/A converter
6. Direct memory access
7. Parallel I/O ports
8. Memory component interface
9. Software debug support

• Microcontrollers have been used in almost every product that requires a certain
amount of intelligence.
• Microcontrollers have been used as controllers for displays, printers, keyboards,
modems, charge card phones, palm-top computers, home appliances such as
washing machines and microwave ovens, automobile control, and so on.

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Embedded Systems
• An embedded system is a computer designed to perform a dedicated function.
• An embedded system performs one or a few predefined tasks, with very specific
requirements.
• Embedded systems are often mass-produced and benefitting from economic scale.
• Software written for embedded systems is often called firmware.

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Memory Technologies
Magnetic Memory
• Magnetic drums, magnetic tapes, and magnetic disks are the three major magnetic
memory devices that have been invented.
• Only magnetic disks are still being widely used today
• Hard disks are rarely used in an embedded system

Optical Memory
• Compact disk (CD) and digital video disc (DVD) are two major optical memory devices.
• CD was introduced in 1982.
• CD has two versions: CD-R and CD-RW.
• The capacity of a 12-inch CD is 700 MB.
• A 12-inch DVD has the capacity of 4.7 GB
• DVD has two versions: DVD-R and DVD-RW versions.

Semiconductor Memory
• Semiconductor memory can be classified on the basis of volatility and read-writability.
• On the basis of volatility, semiconductor memory is divided into volatile and
non-volatile memory.
• On the basis of read-writability, semiconductor memory is divided into random-access
memory (RAM) and read-only memory (ROM).

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Random-access memory
There are four types of RAM:

Dynamic random-access memory (DRAM):

• The one-bit cell of DRAM consists of one transistor and one capacitor.
• The information is stored in the capacitor whereas the transistor controls the access of
the information stored in the capacitor.
• Periodic refresh is required to maintain the contents of a DRAM chip

Static random-access memory (SRAM):

• The one-bit of SRAM consists of 4 to 6 transistors.
• No periodic refresh operation is required to maintain the information stored in SRAM.

Magneto RAM (MRAM):

• The one-bit cell of MRAM consists of two magnetic plates each of which can hold a
magnetic field, separated by a thin insulating layer. One of the plates is a permanent
magnet set to a particular polarity.
• A MRAM chip combines a magnetic device with standard silicon-based microelectronics
to achieve the attributes of non-volatility, high-speed operation, and unlimited read and
write endurance

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Ferroelectric RAM (FRAM)

• FRAM uses the state change of ferroelectric crystal to store information.
• FRAM technology is mainly developed by Ramtron International.
• FRAM is nonvolatile and has an access time about 55 ns in 2007.
• Due to its lower density, FRAM is mainly used in niche applications.

Read-Only Memory
• ROM is nonvolatile.
• There are several types of ROM technologies.

Mask-Programmed ROM (MROM)

• The contents of MROM is programmed when it is manufactured.
• To be cost-effective, many thousands of copies of MROM chip must be manufactured.
• MROM is one of the major ROM technologies to hold application programs

Programmable ROM (PROM)

• PROM was invented in 1956 by Win-Tsing Chow.
• The setting of each bit is locked by a fuse or antifuse.
• PROM is programmed by blowing a fuse or an antifuse.
• PROM can only be programmed once using a special programmer.

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Erasable programmable ROM (EPROM)

• EPROM was invented by an Israelis engineer Dov Frohman in 1971.
• An EPROM cell must be erased before it is programmed.
• EPROM is electrically programmable many times.
• EPROM is erased by ultraviolet light (through a window).
• EPROM can only be erased in bulk (whole chip in one erasure operation).

Electrically erasable programmable ROM (EEPROM)

• EEPROM was invented by George Perlegos of Intel in 1983.
• An EEPROM cell must be erased before it is programmed.
• EEPROM is electrically erasable and programmable many times.
• EEPROM can be erased one location, one row, or whole chip in one operation

Flash memory
• Flash memory was invented by Fujio Masuoka in 1984.
• Flash memory is electrically erasable and programmable many times.
• Flash memory can only be erased in bulk or a sector at a time
• Flash can achieved the density of DRAM and is the most widely used nonvolatile memory
technology.

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Computer software

• Computer programs are known as software

• A program is a sequence of instructions

Machine instruction

• A sequence of binary digits which can be executed by the processor

0001 1000 0000 0110: A  [A] + [B]

0100 0011: A  [A] + 1
1000 0110 0000 0110: A  6

• Hard to understand, enter, debug, and maintain for human being

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Assembly language

• Defined by assembly instructions

• An assembly instruction is a mnemonic representation of a machine instruction

ABA: A  [A] + [B]

DECA: A  [A] – 1

• Assembly programs must be translated into machine instructions before it can be

executed -- translated by an assembler
• There are two kinds of assembler: native assembler and cross assembler.
• Programmers need to work on the program logic at a very low level and cannot
achieve high productivity.

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High-level language
• Syntax of a high-level language is similar to English
• A translator (called compiler) is required to translate the program written in a high-level
language:

1. There are two types of compilers: native compiler and cross compiler.
2. High-level languages allow the user to work on the program logic at higher level
and achieve higher productivity.

Source code
• A program written in assembly or high-level language

Object code
• The output of an assembler or compiler

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line addr. machine code source code

1: = 00002000 org $2000

2: 2000 B6 1000 ldaa $1000
3: 2003 BB 1001 adda $1001
4: 2006 BB 1002 adda $1002
5: 2009 7A 1100 staa $1100
6: end

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Memory System Operation

• A block diagram of a memory system is shown in Figure 1.2.
• Each memory location has two components: address and contents.
• The organization of a memory chip is indicated by m x n, where m is
the number of locations in the chip and n indicates the number of bits in one location.
• The notation [reg] and [addr] specifies the contents of a register and the memory location
at addr, respectively.

Microprocessor Memory system

address

RD OE
W
WE
R

data

Figure 1.2 Block diagram of a simplified memory system

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Read Operation
• The processor places the address of the memory location that it intends to read on
the address bus and asserts the RD signal.
• The RD signal enables the memory chip to send out the contents of the selected location
on the data bus and the processor gets the data.

Write Operation
• The processor places the address of the location that it intends to write on the address
bus.
• The processor also places the data that it intends to write on the data bus and asserts
the WE signal.
• In responds to the WE signal, the memory chip stores the data on the data bus in the
selected memory location.

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Program Execution
To understand how processor executes the program, we need to answer the following
questions:

Where does the processor start to execute program after power on?
• From a fixed location such as address 0: PIC18, Atmel avr, and 8051
• Fetch the starting address from a fixed location: HCS12

How does the processor update the program counter (PC)?

• Increment the program counter by the length of the instruction just executed.
• Increment or decrement by the amount specified in the current instruction—conditional
and unconditional branch instructions.
• Set to the new address specified by the current instruction—jump (or goto) instruction or
subroutine call instruction.

Program Counter Circuit

• A common building block of PC is the D flip-flop with set and reset capability (Figure 1.3).
• The program counter circuit that can be forced to 0, incremented by 1, incremented by
a field in the instruction, and loaded with a jump target is shown in Figure 1.4.

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D Q

CLK

set reset

Figure 1.3 Block dia gra m of a D flip-flop with set a nd reset

1 Bra nch
offset
0 1
Bra nch
MUX1 16

a dder Qs
16 CLK Clk
PC
MUX2
16
1 0

Jump 16 Ds Power
reset
ta rget On

Jump
Figure 1.4 A simplified block dia gra m of the progra m counter (PC)
of a n 8-bit microcontroller

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Architecture of the Processor X

• Processor X has a separate data memory and program memory spaces.
• Processor X is used to explain the instruction execution process.
• The instruction set of processor X is given in Table 1.3.
• Processor X has an 8-bit accumulator A and a 16-bit register ptr.
• Processor X instructions can use an 8-bit value to specify a data memory location from
0 to 255 to be accessed.
• For data memory locations with address higher than 255, the processor uses the 16-bit
register ptr to specify the address.
• Processor X uses a MDR register to hold data to be written and read from data memory.
• The instruction set implemented by processor X is given in Table 1.3.

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Ta ble 1.3 The instruction set of the processor X

Assembly instruction Ma chine
mea ning
mnemonic code
ld addr,#val 75 aa xx Loa d the 8-bit va lue (val) into memory loca tion a t a ddr.
ld ptr,#data16 90 yyyy Loa d the 16-bit va lue (da ta 16) into the register ptr.
ld A,@ptr E0 Loa d the contents of memory loca tion pointed to by ptr into A.
and A,#val 54 xx And the 8-bit va lue (va l) with A a nd lea ve the result in A.
bnz addr,offset 70 zz Bra nch to a loca tion tha t is offset from the next instruction if the va lue a t a ddr is zero.
inc addr 05 aa Increment the contents of memory loca tion a t a ddr.
dbnz addr,offset D5 aa zz Decrement the contents of memory loca tion a t a ddr a nd bra nch if the result is not
zero. The bra nch dista nce is offset.
Note:
a a : a n 8-bit va lue tha t represent a n 8-bit a ddress
xx : a n 8-bit va lue
yyyy: a 16-bit va lue
zz: dista nce of bra nch from the first byte of the instruction a fter the bra nch instruction .
Ma chine code a re expressed in hex forma t.

Instruction sequence example

ld 0x20,#0 ; place 0 in data memory at 0x20

ld 0x21,#20 ; place 20 in data memory at 0x21
ld ptr,#0x2000 ; load 0x2000 into the ptr register
loop: ld A,@ptr ; load the memory contents pointed to by ptr
and A,#0x03 ; and the value 0x03 with accumulator A
bnz next ; branch if the result is not 0
inc 0x20 ; increment the memory location at 0x20 by 1
next: dbnz 0x21,loop ; decrement memory location at 0x21 and branch
; if the contents of 0x21 is not zero yet

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Instruction Execution Process

Assume that processor X executes the instruction sequence in the previous out of reset.

Instruction ld 0x20,#0 (machine code 75 20 00)

Step 1
Processor X places 0 (contents of PC) on the address bus to perform a read from program
program memory.
Step 2
The 8-bit value at the location 0x0000 is the instruction opcode 0x75. At the end of this
read cycle, the PC is incremented to 0x0001. The opcode byte 0x75 is fetched.
Figure 1.5 shows the opcode read cycle.
Step 3
Recognizing that 0x75 is the opcode of a load instruction, processor performs two more read
operations. The first read returns the address 0x20 whereas the second read returns the
value 0.
Step 4
Processor places 0x20 on the data memory address bus and places 0 on the data bus and
then performs a write operation to write the value 0 to location 0x20.

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Da ta meory
Progra m memory
Address bus 75 Da ta memory
0 x0 0 0 0 20 Address bus xx
00 0 x20 xx
75
xx
21
xx
14
xx
90
xx
CPU 20
xx
00
E0 CPU xx
54 xx
03 xx
Before rea d 70 Before write xx
0 x75 02 xx
0 x0 00 0 Progra m memory 05 0 x0 0 03
xx
PC da ta bus 20 PC 0x75
0 x0 0 xx
After rea d D5 Da ta memory xx
After write
21 da ta bus xx
0x0 0 0 1 0 x0 0 03
0A xx
PC PC
Figure 1.5 Instruction 1—opcode rea d cycle Figure 1.6 Instruction 1—da ta memory write cycle

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Instruction ld 0x21,#20 (machine code 75 21 14)

• The execution of this instruction is identical to that of the previous instruction.
• PC is incremented to 0x0006 after the execution of this instruction.

Instruction ld ptr,#0x2000 (machine code 90 20 00)

Step 1
Processor X places the PC value (0x06) on the program memory address bus and makes
request to read the program memory. Figure 1.7 shows the opcode read cycle.
Step 2
The opcode returned from location at 0x06 is 0x90 and PC is incremented to 0x07.
Step 3
The opcode 0x90 indicates that processor X should access program memory to fetch the
16-bit value stored after the opcode byte. Processor performs two more read cycles from
program memory and places these two bytes in the ptr register. PC is incremented to 0x09.

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Progra m memory
Address bus 75
0 x0 0 0 6 20
00
75
21
14
90
CPU 20
00
E0
54
03
Before rea d 70
0 x90 02
0 x0 0 06
Progra m memory 05
PC da ta bus 20
After rea d D5
21
0 x00 07
0A
PC

Figure 1.7 Instruction 3—opcode rea d cycle

Instruction ld A,@ptr (machine code E0)

Step 1
Processor X places the PC value (0x09) on the program memory address bus and requests
to read the program memory. At the end of this step, PC is incremented to 0x0A.

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Step 2
The opcode (0xE0) returned in Step 1 requires the processor to perform a read operation
Using the address stored in ptr register. Processor X places the contents of ptr register
on the data memory address bus and request a read operation.
Step 3
Data memory returns the byte in data memory pointed to by ptr register. This byte is
placed in A.
Da ta meory

Da ta memory
Address bus xx
[ptr] xx
xx
xx
xx
xx
xx
CPU xx
xx
xx
xx
[ptr]: contents of ptr xx
xx
Mem[[ptr]]: contents of memory
Mem[[ptr]] xx
loca tion pointed to by ptr
Da ta memory xx
da ta bus xx
xx

Figure 1.8 Instruction 4—da ta memory rea d cycle

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Instruction and A,#0x03 (machine code 54 03)

Step 1
Processor X places the PC value on the program memory address bus to request a read.
After this step is completed, PC is incremented to 0x0B.
Step 2
The opcode byte (0x54) returned in Step 1 requires the processor X to perform another
read operation from program memory.
Step 3
Processor X places the PC value on program memory address bus and request to perform
a read operation. PC is incremented to 0x0C after this step.
Step 4
Program memory returns the value 0x03 to the processor.
Step 5
The processor X then performs an AND operation on the contents of A and the value 0x03
and places the result in A

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Instruction bnz next (machine code is 70 02)

Step 1
Processor X places the PC value (0x0C) on the program memory address bus and performs
a read operation. After this step, PC is incremented to 0x0D.
Step 2
The opcode (0x70) returned in Step 1 requires processor X to performs another read to
fetch the branch offset.
Step 3
Processor X places the value PC (0x0D) on the program memory address bus and performs
a read. After this step the program memory returns the value 0x02 to the processor. PC
is incremented to 0x0E.
Step 4
Processor checks whether the A value is zero and decides whether branch should be
taken. If A contains a nonzero value, the next instruction will be skipped.

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Instruction inc 0x20 (machine code 05 20)

Step 1
Processor X places the PC contents (0x0E) on the program memory address bus and
Performs a read operation. At the end of the read operation, PC is incremented to 0x0F.
Step 2
The returned opcode (0x05) requires processor X to performs another read to fetch an
8-bit address from program memory.
Step 3
Processor X places the contents of PC on the program memory address bus to request
another read from program memory. PC is incremented to 0x10
Step 4
Processor X places the value 0x20 on the data memory address bus and requests a read.
The returned value is placed in MDR register.
Step 5
Processor X adds one to the MDR register.
Step 6
Processor X places the contents of MDR on data memory data bus and 0x20 on the address
bus and requests a write operation. At the end the value in MDR register is written into
data memory location at 0x20.

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Instruction dbnz 0x21, loop (machine code is D5 21 0A)

Step 1
Processor X places the contents of PC on the program memory address bus and requests
a read operation. At the end of this step PC is incremented to 0x11.
Step 2
The opcode (0xD5) returned in step 1 request processor X to perform two more read
operation to fetch a byte of data memory address and a byte of branch offset from
program memory. At the end of these two read operations, PC is incremented to 0x13.
Step 3
Processor places the value of 0x21 on the data memory address bus to perform a read.
At the end of this read, the contents of data memory location at 0x21 is returned in MDR.
Step 4
Processor decrements the contents of MDR by 1 and then places this result on the data
memory data bus. At the same time, it also places the value of 0x21 on the data memory
address bus and requests a write operation.
Step 5
If the value stored in MDR is not zero, processor X adds 0x0A to the PC and places the sum
back in PC (this causes a branch). Otherwise, PC is not changed.

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The HCS12 Features

• 16-bit CPU
• 64 KB memory space (also supports expanded memory up to 1 MB through
a 16-KB window)
• 0 KB to 4KB of EEPROM
• 2KB to 14KB of on-chip SRAM
• 32 KB to 512KB flash memory
• Sophisticated timer functions that include: input capture, output compare,
pulse accumulators, real-time interrupt, and COP timer
• Serial communication interfaces: SCI, SPI, CAN, BDLC
• Background debug mode (BDM)
• 10-bit A/D converter
• Instructions for supporting fuzzy logic function

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The HCS12 CPU Registers

7 A 0 7 B 0 8-bit a ccumula tor A a nd B

or
15 D 0
16-bit double a ccumula tor D

15 X 0 Index register X

15 Y 0 Index register Y

15 SP 0 Sta ck pointer

15 PC 0 Progra m counter

S X H I N Z V C Condition code register

Ca rry
Overflow
Zero
Nega tive
I Interrupt ma sk
Ha lf-Ca rry (from bit 3)
X Interrupt Ma sk
Stop Disa ble

Figure 1.10 HCS12 CPU registers.

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The HCS12 Addressing Modes

• A HCS12 instruction consists of one or two bytes of opcode and zero to five bytes of
operand addressing information.
• Opcode bytes specify the operation to be performed by the CPU. The first byte of a two-
byte opcode is always $18.
• Addressing modes specify the operand to be operated on.
• The addressing mode may specify a value, a register, or a memory location to be used as
an operand.

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Table 1.2P M68HC12 addressing mode summary
Addressing mode Source format Abbre. Description
Inherent INST INH Operands (if any) are in CPU registers
(no externally
supplied operands)
Immediate INST #opr8i IMM Operand is included in instruction stream. 8- or 16-
or bit size implied by context
INST #opr16i
Direct INST opr8a DIR Operand is the lower 8 bits of an address in the
range $0000-$00FF
Extended INST opr16a EXT Operand is a 16-bit address
Relative INST rel8 An 8-bit or 16-bit relative offset from the current
or REL PC is supplied in the instruction
INST rel16
Indexed INST oprx5,xysp IDX 5-bit signed constant offset from x,y,sp, or pc
(5-bit offset)
Indexed INST oprx3,-xys IDX Auto pre-decrement x, y, or sp by 1 ~ 8
(pre-decrement)
Indexed INST oprx3,+xys IDX Auto pre-increment x, y, or sp by 1 ~ 8
(pre-increment)
Indexed INST oprx3,xys- IDX Auto post-decrement x, y, or sp by 1 ~ 8
(post-decrement)
Indexed INST oprx3,xys+ IDX Auto post-increment x, y, or sp by 1 ~ 8
(post-increment)
Indexed INST abd,xysp IDX Indexed with 8-bit (A or B) or 16-bit (D)
(accumulator offset) accumulator offset from x, y, sp, or pc
Indexed INST oprx9,xysp IDX1 9-bit signed constant offset from x, y, sp, or pc
(9-bit offset) (lower 8-bits of offset in one extension byte)
Indexed INST oprx16,xysp IDX2 16-bit constant offset from x, y, sp, or pc (16-bit
(16-bit offset) offset in two extension bytes)
Indexed-Indirect INST [oprx16,xysp] [IDX2] Pointer to operand is found at 16-bit constant offset
(16-bit offset) from (x, y, sp, or pc)
Indexed-Indirect INST [D,xysp] [D,IDX] Pointer to operand is found at x, y, sp, or pc plus
(D accumulator the vlaue in D
offset)

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Inherent Mode
- Instructions that use this mode do not uses extra bytes to specify operands because
the instructions either do not need operands or all operands are CPU registers.
- Operands are implied by the opcode.
- Examples

NOP
INX
DECA

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Immediate Mode
- Operands for instructions that use immediate mode are included in the instruction.
- CPU does not access memory for operands.
- For example,
LDAA #$55
LDX #$1000

Direct Mode
- This mode can only specify memory locations in the range of 0 - 255.
- This mode uses only one byte to specify the operand address.
- Examples,
LDAA $20
LDAB $40

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Extended Mode
- This mode uses a 16-bit value to specify memory address is in the instruction.
- For example,
LDAA $4000 ; A ← [$4000]
LDX $FE60 ; X ← [$FE60]:[$FE61]
Relative Mode
- Used only by branch instructions.
- Short and long conditional branch instructions use exclusively relative mode.
- BRCLR and BRSET instructions can also use relative mode to specify branch target.
- A short branch instructions consists of an 8-bit opcode and a signed 8-bit offset. The
short relative mode can specify a range of -128 ~ +127.
- A long branch instruction consists of an 8-bit opcode and a signed 16-bit offset. The
range of the long relative mode is from -32768 ~ +32767.
- A programmer uses a symbol to specify the branch target and the assembler will figure
out the actual branch offset (distance) from the instruction that follows branch
instruction.
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- For example,
minus …
…
bmi minus
…
Indexed Mode
- This mode uses the sum of an index register (X, Y, PC, or SP) and an offset to specify the
address of an operand.
- The offset can be a 5-bit, 9-bit, and 16-bit signed value or the value in accumulator A,
B, or D.
- Automatic pre- or post-increment or pre- or post-decrement by -8 to +8 are options.
- PC can be used as the index register for all but auto-increment or auto-decrement mode.
- Indirect indexing with 16-bit offset or accumulator D as the offset is supported.

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5-bit Constant Offset Indexed Addressing

- The base index register can be X, Y, SP, or PC.
- The range of the offset is from -16 to +15.
- Examples,
ldaa 0,X
stab -8,0
9-bit Constant Offset Indexed Addressing
- The base index register can be X, Y, SP, or PC.
- The range of the offset is from -256 to +255.
- Examples,
ldaa $FF,X
ldab -20,Y

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16-bit Constant Offset Indexed Addressing

- The base index register can be X, Y, SP, or PC.
- This mode allows access any location in the 64-KB range.
- Examples,
ldaa 2000,X
staa 4000,Y
16-bit Constant Indirect Indexed Addressing
- A 16-bit offset is added to the base index register to form the address of a memory
location that contains a pointer to the memory location affected by the instruction.
- The square brackets distinguish this addressing mode from the 16-bit constant offset
indexing. For example,
ldaa [10,X]
staa [20,Y]

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Auto Pre/Post Decrement/Increment Indexed Addressing

- The base index register can be X, Y, or SP.
- The index register can be incremented or decremented by an integer value either
before or after indexing taking place.
- The index register retains the changed value after indexing.
- The value to be incremented or decrement is in the ranges -8 thru -1 or 1 thru 8.
- The value need to be related to the size of the operand or the current instruction.
- Examples,
staa 1,-SP ; decrement SP by 1 and then store the contents of A in the location
; pointed to by SP and
staa 1,SP- ; store the contents of A in the location pointed by SP and then
; decrement SP by 1
ldx 2,+SP
ldx 2,SP+

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Accumulator Offset Indexed Addressing

- The effective address of the operand is the sum of the accumulator and the base index
register.
- The base register can be X, Y, SP, or PC.
- The accumulator can be the 8-bit A or B or the 16-bit accumulator D.
- For example,
ldaa B,X
stab B,Y
ldy D,X

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Accumulator D Indirect Indexed Addressing

- The value in D is added to the value in the base index register to form the address of
the memory location that contains the address to the memory location affected by the
instruction.
- The square brackets distinguish this addressing mode from accumulator D offset
indexing. For example,
jmp [D,PC]
go1 dc.w target1
go2 dc.w target2
go3 dc.w target3
…
target1 …
.
target2 …
.
target3 …

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HCS12 Instruction Examples

The LOAD and STORE Instructions
- The LOAD instruction copies the contents of a memory location or places an immediate
value into an accumulator or a CPU register.
- STORE instructions save the contents of a CPU register into a memory location.
- N and Z flags of the CCR register are automatically updated and the V flag is cleared.
- All except for the relative mode can be used to select the memory location or value to
be loaded into an accumulator or CPU register.
- All except for the relative and immediate modes can be used to select memory location
to store contents of the CPU register. For example,
ldaa 0,X
staa $20
stx $8000
ldd #100

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Ta ble 1.4 Loa d a nd store instructions

Loa d Instructions
Mnemonic Function Opera tion
lda a <opr> Loa d A A ¬ [opr]
lda b <opr> Loa d B B ¬ [opr]
ldd <opr> Loa d D A:B ¬ [opr]:[opr+1]
lds <opr> Loa d SP SP ¬ [opr]:[opr+1]
ldx <opr> Loa d index register X X ¬ [opr]:[opr+1]
ldy <opr> Loa d index register Y Y ¬ [opr]:[opr+1]
lea s <opr> Loa d effective a ddress into SP SP ¬ effective a ddress
lea x <opr> Loa d effective a ddress into X X ¬ effective a ddress
lea y <opr> Loa d efective a ddress into Y
Y ¬ effective a ddress
Store Instructions
Mnemonic Function Opera tion
sta a <opr> Store A in a memory loca tion m[opr] ¬ [A]
sta b <opr> Store B in a memory loca tion m[opr] ¬ [B]
std <opr> Store D in a memory loca tion m[opr]:m[opr+1] ¬ [A]:[B]
sts <opr> Store SP in a memory loca tion m[opr]:m[opr+1] ¬ [SP]
stx <opr> Store X in a memory loca tion m[opr]:m[opr+1] ¬ [X]
sty <opr> Store Y in a memory loca tion m[opr]:m[opr+1] ¬ [Y]

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Transfer and Exchange Instructions

- Transfer instructions copy the contents of a CPU register or accumulator into another
CPU register or accumulator.
- TFR is the universal transfer instruction, but other mnemonics are accepted for
compatibility with the 68HC11.
- The TAB and TBA instructions affect the N, Z, and V condition code bits.
- The TFR instruction does not affect any condition code bits. For example,
TFR D,X ; [D]  X
TFR A,B ; [A]  B
TFR A,X ; sign-extended of[A]  X ; A is signed extended to 16-bit and
assigned to X
TFR X,A ; X[7:0]  A ; lower 8 bits copied to A

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- The EXG instruction exchanges the contents of a pair of registers or accumulators. For
example,
exg A, B
exg D,X
exg A,X ; A  X[7:0], X  $00:[A]
exg X,B ; X  $00:[B], B  X[7:0]

- The SEX instruction sign-extend an 8-bit two’s complement number into a 16-bit
number so that it can be used in 16-bit signed operations. For example,
SEX A,X

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Move Instructions
- These instructions move data bytes or words from a source to a destination in memory.
- Six combinations of immediate, extended, and index addressing modes are allowed to
specify the source and destination addresses:
IMM  EXT, IMM  IDX, EXT  EXT,
EXT  IDX, IDX  EXT, IDX  IDX
- For example,
movb $100,$800
movw 0,X, 0,Y

Ta ble 1.6 Move instructions

Tra nsfer Instructions
Mnemonic Function Opera tion
movb <src>, <dest> Move byte (8-bit) dest ¬ [src]
movw <src>, <dest> Move word (16-bit) dest ¬ [src]

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Add and Subtract Instructions

- These instructions perform fundamental arithmetic operations.
- The destinations of these instructions are always a CPU register or accumulator.
- There are two-operand and three-operand versions of these instructions.
- Three-operand ADD or SUB instructions always include the C flag as one of the
operand.
- Three-operand ADD or SUB instructions are used to perform multi-precision addition
or subtraction.
- For example,
adda $1000 ; A  [A] + [$1000]
adca $1000 ; A  [A] + [$1000] + C
suba $1002 ; A  [A] + [$1002]
sbca $1000 ; A  [A] - [$1000] - C

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Ta ble 1.7 Add a nd subtra ct instructions

Add Instructions
Mnemonic Function Opera tion
a ba Add B to A A¬ [A] + [B]
a bx Add B to X X¬ [X] + [B]
a by Add B to Y Y¬ [Y] + [B]
a dca <opr> Add with ca rry to A A¬ [A] + [opr] + C
a dcb <opr> Add with ca rry to B B¬ [B] + [opr] + C
a dda <opr> Add without ca rry to A A¬ [A] + [opr]
a ddb <opr> Add without ca rry to B B¬ [B] + [opr]
a ddd <opr> Add without ca rry to D D¬ [D] + [opr]
Subtra ct Instructions
Mnemonic Function Opera tion
sba Subtra ct B from A A¬ [A] - [B]
sbca <opr> Subtra ct with borrow from A A¬ [A] - [opr] - C
sbcb <opr> Subtra ct with borrow from B B¬ [B] - [opr] - C
suba <opr> Subtra ct memory from A A¬ [A] - [opr]
subb <opr> Subtra ct memory from B B¬ [B] - [opr]
subd <opr> Subtra ct memory from D D¬ [D] - [opr]

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Instruction Execution Cycle

- One or more read cycles to fetch instruction opcode bytes and addressing information.
- One or more read cycles to fetch the memory operand(s) (optional).
- Perform the operation specified by the opcode.
- One or more write cycles to write back the result to either a register or a memory
- location (optional).
Instruction Queue
- The HCS12 executes one instruction at a time and many instructions take several clock
cycles to complete.
- When the CPU is performing the operation, it does not need to access memory.
- The HCS12 pre-fetches instructions when the CPU is not accessing memory to speedup
the instruction execution process.
- There are two 16-bit queue stages and one 16-bit buffer. Unless buffering is required,
program information is first queued in stage 1, and then advanced to stage 2 for
execution.

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