Introduction to VHDL

Prepared by : VISHAL MOYAL (Associate Professor and Head ,ET)

VISHAL MOYAL/VHDL 1
 What Is VHDL?
VHDL is an acronym for

VHSlC Hardware Description Language

(VHSIC is an acronym for Very High Speed

Integrated Circuits).

VISHAL MOYAL/VHDL 2
 What Is VHDL?
sequential language +

concurrent language +

net-list language +

timing specifications +

waveform generation language => VHDL

VISHAL MOYAL/VHDL 3
 History
Generated in 1981 under the VHSIC
program.

Version 7.2 was developed and released to

the public in 1985.

Transferred to the IEEE for standardization

in 1986.
VISHAL MOYAL/VHDL 4
 History
the language was standardized by the IEEE
in December 1987

known as the IEEE Std 1076-1987.

VISHAL MOYAL/VHDL 5
 Capabilities
The language can be used as an exchange
medium between chip vendors and CAD
tool users.

The language can also be used as a

communication medium between different
CAD and CAE tools

VISHAL MOYAL/VHDL 6
 Capabilities
The language supports hierarchy.

The language supports flexible design

methodologies: top-down, bottom-up, or
mixed.

The language is not technology-specific

VISHAL MOYAL/VHDL 7
 Capabilities
It supports both synchronous and
asynchronous timing models.

Various digital modeling techniques such as

finite-state machine descriptions,
algorithmic descriptions, and Boolean
equations can be modeled using the
language.
VISHAL MOYAL/VHDL 8
 Capabilities
The language is publicly available, human
readable, machine readable, and above all,
it is not proprietary.

It is an IEEE and ANSI standard

VISHAL MOYAL/VHDL 9
 Capabilities
The language supports three basic different
description styles: structural, dataflow, and
behavioral.

It supports a wide range, of abstraction

levels ranging from abstract behavioral
descriptions to very precise gate-level
descriptions.
VISHAL MOYAL/VHDL 10
 Capabilities
The language has elements that make large
scale design modeling easier, for example,
components, functions, procedures, and
packages.

There is no need to learn a different

language for simulation control. Test
benches can be written using the same
language to test other VHDL models.
VISHAL MOYAL/VHDL 11
 Capabilities
Nominal propagation delays, min-max
delays, setup and hold timing, timing
constraints, and spike detection can all be
described very naturally in this language.

The use of generics and attributes in the

models facilitate back-annotation of static
information such as timing or placement
information.
VISHAL MOYAL/VHDL 12
 Capabilities
Models written in this language can be
verified by simulation since precise
simulation semantics are defined for each
language construct.

Behavioral models that conform to a certain

synthesis description style are capable of
being synthesized to gate-level descriptions.
VISHAL MOYAL/VHDL 13
 Capabilities
The capability of defining new data types
provides the power to describe and simulate
a new design technique at a very high level
of abstraction without any concern about
the implementation details.

VISHAL MOYAL/VHDL 14
 Hardware Abstraction

VISHAL MOYAL/VHDL 15
 Hardware Abstraction

VISHAL MOYAL/VHDL 16
 Basic Terminology
1. Entity declaration

2. Architecture body

3. Configuration declaration

4. Package declaration

5. Package body
VISHAL MOYAL/VHDL 17
 Entity Declaration

VISHAL MOYAL/VHDL 18
 Entity Declaration
The entity declaration specifies the name of
the entity being modeled and lists the set
of interface ports.

Ports are signals through which the entity

communicates with the other models in its
external environment.

VISHAL MOYAL/VHDL 19
 Entity Declaration

entity HALF_ADDER is
port (A, B: in BIT; SUM, CARRY: out BIT);
end HALF_ADDER;
-- This is a comment line.
VISHAL MOYAL/VHDL 20
 Entity Declaration

entity DECODER2x4 is
port (A, B, ENABLE: in BIT;
Z: out BIT_VECTOR(0 to 3));
end DECODER2x4;
VISHAL MOYAL/VHDL 21
 Architecture Body
1. As a set of interconnected components
(to represent structure),

2. As a set of concurrent assignment

statements (to represent dataflow),

3. As a set of sequential assignment

statements (to represent be-hav.ior),

4.VISHAL
Any combination of the above three.
MOYAL/VHDL 22
 Dataflow Style
architecture HA_CONCURRENT of HALF_ADDER is
begin
SUM <= A xor B after 8 ns;
CARRY <= A and B after 4 ns;
end HA_CONCURRENT;

VISHAL MOYAL/VHDL 23
 Dataflow Style
architecture dec_dataflow of DECODER2x4 is
signal ABAR, BBAR: BIT;
begin
Z(3) <= not (A and B and ENABLE);
Z(0) <= not (ABAR and BBAR and ENABLE);
BBAR <= not B;
Z(2) <= not (A and BBAR and ENABLE);
ABAR <= not A;
Z(1 ) <= not (ABAR and B and ENABLE);
end DEC_DATAFLOW;
VISHAL MOYAL/VHDL 24
 Dataflow Style
CLK <= not CLK after 20 ns;

VISHAL MOYAL/VHDL 25
 Structural Style
architecture HA_STRUCTURE of HALF_ADDER is
component XOR2
port (X, Y: in BIT; Z: out BIT);
end component;
component AND2
port (L, M: in BIT; N: out BIT);
end component;
begin
X1: XOR2 port map (A, B, SUM);
A1: AND2 port map (A, B, CARRY);
end HA_STRUCTURE;
VISHAL MOYAL/VHDL 26
 Structural Style
architecture DEC_STR of DECODER2x4 is
component INV
port (A: in BIT; Z: out BIT);
end component;

component NAND3
port (A, B, C: in BIT; Z: out BIT);
end component;

signal ABAR, BBAR: BIT;

begin
VISHAL MOYAL/VHDL 27
 Structural Style
I0: INV port map (A, ABAR);
I1: INV port map (B, BBAR);
N0: NAND3 port map (ABAR, BBAR, ENABLE, Z(0));
N1: NAND3 port map (ABAR, B, ENABLE, Z(1));
N2: NAND3 port map (A, BBAR, ENABLE, Z(2));
N3: NAND3 port map (A, B, ENABLE, Z(3));
end DEC_STR;

VISHAL MOYAL/VHDL 28
 Behavioral Style
architecture DEC_SEQUENTIAL of DECODER2x4 is
begin
process (A, B, ENABLE)
variable ABAR, BBAR: BIT;
begin
ABAR := not A;
BBAR := not B;

VISHAL MOYAL/VHDL 29
 Behavioral Style
if (ENABLE = '1') then
Z(3) <= not (A and B);
Z(0) <= not (ABAR and BBAR);
Z(2) <= not (A and BBAR);
Z(1 ) <= not (ABAR and B);
else
Z<= "1111";
end if;
end process;
End DEC_SEQUENTIAL;
VISHAL MOYAL/VHDL 30
 Behavioral Style
process
begin
CLK <= '0' ;
wait for 20 ns;
CLK <= '1' ;
wait for 12 ns;
end process;

VISHAL MOYAL/VHDL 31
 Behavioral Style
entity LS_DFF is
port (Q: out BIT; D, CLK: in BIT):
end LS_DFF;

architecture LS_DFF_BEH of LS_DFF is

begin
process (D, CLK)
begin

VISHAL MOYAL/VHDL 32
 Behavioral Style
if (CLK = '1') then
Q <= D;
end if;
end process;
end LS_DFF_BEH;

VISHAL MOYAL/VHDL 33
 Mixed Style

VISHAL MOYAL/VHDL 34
 Mixed Style
entity FULL_ADDER is
port (A, B, CIN: in BIT;
SUM, COUT: out BIT);
end FULL_ADDER;

architecture FA_MIXED of FULL_ADDER is

component XOR2
port (A, B: in BIT; Z: out BIT);
end component;
signal S1: BIT;
VISHAL MOYAL/VHDL 35
 Mixed Style
begin
X1: XOR2 port map (A, B, S1 ); - structure.

process (A, B, CIN) - behavior.

variable T1, T2, T3: BIT;
begin
T1 :=A and B;
T2 := B and CIN;
T3:=A and CIN;
COUT <= T1 or T2 or T3;
end
VISHALprocess;
MOYAL/VHDL 36
 Mixed Style
SUM <= S1 xor CIN; - dataflow.
end FA_MIXED;

VISHAL MOYAL/VHDL 37
 Configuration Declaration
Used to create a configuration for an entity.

It specifies the binding of one architecture

body from the many architecture bodies
that may be associated with the entity.

It may also specify the bindings of

components used in the selected
architecture body to other entities.
VISHAL MOYAL/VHDL 38
 Configuration Declaration

VISHAL MOYAL/VHDL 39
 Configuration Declaration
library CMOS_LIB, MY_LIB;
configuration HA_BINDING of HALF_ADDER is
for HA-STRUCTURE
for X1:XOR2
use entity CMOS_LIB.XOR_GATE(DATAFLOW);
end for;

for A1:AND2
use configuration MY_LIB.AND_CONFIG;
end for;
end for;
end HA_BINDING;
VISHAL MOYAL/VHDL 40
 Package Declaration &
Package Body
A package declaration encapsulates a set of
related declarations such as type
declarations, subtype declarations, and
subprogram declarations that can be
shared across two or more design units.

A package body contains the definitions of

subprograms declared in a package
declaration.
VISHAL MOYAL/VHDL 41
 Package Declaration &
Package Body
package EXAMPLE_PACK is
type SUMMER is (MAY, JUN, JUL, AUG, SEP);

component D_FLIP_FLOP
port (D, CK: in BIT; Q, QBAR: out BIT);
end component;

constant PIN2PIN_DELAY: TIME := 125 ns;

function INT2BIT_VEC (INT_VALUE: INTEGER)
return BIT_VECTOR;
end EXAMPLE_PACK;
VISHAL MOYAL/VHDL 42
 Package Declaration &
Package Body

VISHAL MOYAL/VHDL 43
 Simulation
The simulator simulates an entity,
represented by an entity-architecture pair or
by a configuration, by reading in its compiled
description from the design library and then
performing the following steps:
1. Elaboration
2. Initialization
3. Simulation

VISHAL MOYAL/VHDL 44
 Simulation
Elaboration phase: In this phase, the
hierarchy of the entity is expanded and
linked.
components are bound to entities in a
library and the top-level entity is built as a
network of behavioral models that is
ready to be simulated.

VISHAL MOYAL/VHDL 45
 Simulation
Initialization phase: The effective
values for all explicitly declared signals are
computed, implicit signals (discussed in
later chapters) are assigned values,
processes are executed once until they
suspend, and simulation time is reset to 0
ns.

VISHAL MOYAL/VHDL 46
 Model Analysis

VISHAL MOYAL/VHDL 47
 Basic Language Elements
Identifiers
Data Objects
Data Types
Operators

VISHAL MOYAL/VHDL 48
 Identifiers
Composed of a sequence of one or more
characters

(A... Z), (a. .. z), (0 . . . 9), ( _ ).

First must be a letter and

Last character may not be an underscore.

VISHAL MOYAL/VHDL 49
 Identifiers
DRIVE_BUS
SelectSignal
RAM_Address
SET_CK_HIGH
CONST32_59
r2d2

VISHAL MOYAL/VHDL 50
 Identifiers
entity UART is end; --This comment starts
after the entity
declaration.

VISHAL MOYAL/VHDL 51
 Identifiers
The language defines a set of reserved
words; called keywords, have a specific
meaning in the language, and therefore,
cannot be used as identifiers.

VISHAL MOYAL/VHDL 52
 Data Objects
Holds a value of a specified type.

Created by means of an object

declaration.

variable COUNT: INTEGER;

VISHAL MOYAL/VHDL 53
 Data Objects
Constant

Variable

Signal

VISHAL MOYAL/VHDL 54
 Data Objects
Constant:
An object of constant class can hold a
single value of a given type.
This value is assigned to the object before
simulation starts and the value cannot be
changed during the course of the
simulation.

VISHAL MOYAL/VHDL 55
 Data Objects

constant RISE_TIME: TIME := 10ns;

constant BUS_WIDTH: INTEGER := 8;

constant NO_OF_INPUTS: INTEGER;

VISHAL MOYAL/VHDL 56
 Data Objects
Variable:
An object of variable class can also hold a
single value of a given type.
However in this case, different values can
be assigned to the object at different
times using a variable assignment
statement.

VISHAL MOYAL/VHDL 57
 Data Objects
Variable CTRL_STATUS:
BIT_VECTOR(10 downto 0);

variable SUM: INTEGER range

O to 100 := 10;

variable FOUND, DONE: BOOLEAN;

VISHAL MOYAL/VHDL 58
 Data Objects
Signal:
An object belonging to the signal class has
a past history of values, a current value,
and a set of future values.
Future values can be assigned to a signal
object using a signal assignment
statement.

VISHAL MOYAL/VHDL 59
 Data Objects
signal CLOCK: BIT;

signal DATA_BUS: BIT_VECTOR

(0 to 7);

signal GATE_DELAY: TIME := 10 ns;

VISHAL MOYAL/VHDL 60
 Data Types
Scalar types:
Values belonging to these types appear in a
sequential order.

Composite types:
These are composed of elements of a single
type (an array type) or elements of different
types (a record type).

VISHAL MOYAL/VHDL 61
 Data Types
Access types:
These provide access to objects of a given
type (via pointers).

File types:
These provides access to objects that
contain a sequence of values of a given type.

VISHAL MOYAL/VHDL 62
 Data Types
Subtypes
A subtype is a type with a constraint.

The constraint specifies the subset of values

for the type.

Subtype declarations are used to declare

subtypes.

VISHAL MOYAL/VHDL 63
 Data Types
An object can be declared to either belong to
a type or to a subtype.
subtype MY_INTEGER is INTEGER range 48 to
156 ;

type DIGIT is ('0', '1', '2', '3', '4', '5', '6', '7', '8',
'9') ;

subtype MIDDLE is DIGIT range '3' to '7' ;

VISHAL MOYAL/VHDL 64
 Data Types
Scalar Types
The values belonging to this type are
ordered, that is, relational operators can be
used on these values.

For example, BIT is a scalar type and the

expression '0' < 1' is valid and has Hie value
TRUE.

VISHAL MOYAL/VHDL 65
 Data Types
There are four different kinds of scalar
types. These types are
1. enumeration,
2. integer,
3. physical,
4. floating point.

VISHAL MOYAL/VHDL 66
 Data Types
Enumeration Types
An enumeration type declaration defines a
type that has a set of user-defined values
consisting of identifiers and character
literals.

VISHAL MOYAL/VHDL 67
 Data Types
type MVL is ('U','0','1','Z);

type MICRO_OP is (LOAD, STORE,

ADD, SUB, MUL, DIV);

subtype ARITH_OP is MICRO_OP range

ADD to DIV;

VISHAL MOYAL/VHDL 68
 Data Types
signal CONTROL_A: MVL;

signal CLOCK: MVL range '0' to '1'; --

Implicit subtype declaration.

variable IC: MICRO_OP := STORE;

-- STORE is the initial value for IC.
variable ALU: ARITH_OP;

VISHAL MOYAL/VHDL 69
 Data Types
Integer Types
An integer type defines a type whose set
of values fall within a specified integer
range.

VISHAL MOYAL/VHDL 70
 Data Types
type INDEX is range 0 to 15;

type WORD_LENGTH is range 31 downto 0;

subtype DATA_WORD is WORD_LENGTH range 15

downto 0;

type MY_WORD is range 4 to 6;

VISHAL MOYAL/VHDL 71
 Data Types

constant MUX_ADDRESS: INDEX := 5;

signal DATA_BUS: DATA_WORD;

VISHAL MOYAL/VHDL 72
 Data Types
Values belonging to an integer type are
called integer literals. Examples of integer
literals are
56349
6E10
98_71_28

VISHAL MOYAL/VHDL 73
 Data Types
Floating point type:
A floating point type has a set of values in
a given range of real numbers.

type TTL_VOLTAGE is range -5.5 to -1.4;

type REAL_DATA is range 0.0 to 31.9;

VISHAL MOYAL/VHDL 74
 Data Types
An example of an object declaration is
variable LENGTH: REAL_DATA range 0.0 to
15.9;

variable LI, L2, L3: REAL_DATA range 0.0 to

15.9;

VISHAL MOYAL/VHDL 75
 Data Types
The range bounds specified in a floating point
type declaration must be constants or locally
static expressions.

Floating-point literals are values of a floating

point type.

16.26 0.0 0.002 3_1.4_2

VISHAL MOYAL/VHDL 76
 Data Types
Physical Types
A physical type contains values that
represent measurement of some physical
quantity, like time, length, voltage, and
current.

Values of this type are expressed as integer

multiples of a base unit.

VISHAL MOYAL/VHDL 77
 Data Types
type CURRENT is range 0 to 1 E9
units
nA; -- (base unit) nano-ampere
uA = 1000 nA; -- micro-ampere
mA = 1000 A; --milli-ampere
Amp = 1000 mA; -- ampere
end units;
subtype FILTER_CURRENT is CURRENT range
10 A to 5 mA;

VISHAL MOYAL/VHDL 78
 Data Types
The only predefined physical type is TIME and
its range of base values.

VISHAL MOYAL/VHDL 79
 Data Types
Composite Types
A composite type represents a collection of
values.

an array type

a record type.

VISHAL MOYAL/VHDL 80
 Data Types
Array Types
An object of an array type consists of elements
that have the same type.

type ADDRESS_WORD is array (0 to 63) of BIT;

type DATA_WORD is array (7 downto 0) of MVL;
type ROM is array (0 to 125) of DATA_WORD;
type DECODE_MATRIX is array (POSITIVE range 15
downto 1);

VISHAL MOYAL/VHDL 81
 Data Types
POSITIVE and NATURAL are predefined subtypes;

subtype NATURAL is INTEGER range 0 to INTEGER'HIGH;

subtype POSITIVE is INTEGER range 1 to INTEGER'HIGH;

VISHAL MOYAL/VHDL 82
 Data Types
Examples of object declarations using these types
are
variable ROM_ADDR: ROM;

signal ADDRESS.BUS: ADDRESS_WORD;

constant DECODER: DECODE_MATRIX;

variable DECODE_VALUE: DECODE_MATRIX;

VISHAL MOYAL/VHDL 83
 Data Types
Record Types
An object of a record type is composed of
elements of same or different types.

VISHAL MOYAL/VHDL 84
 Data Types
Values can be assigned to a record type object
using aggregates.

VISHAL MOYAL/VHDL 85
 Data Types
Access Types:
Values belonging to an access type are pointers to
a dynamically allocated object of some other type.
They are similar to pointers in Pascal and C
languages.

VISHAL MOYAL/VHDL 86
 Data Types
Access Types:
Values belonging to an access type are pointers to
a dynamically allocated object of some other type.
They are similar to pointers in Pascal and C
languages.

VISHAL MOYAL/VHDL 87
 Data Types
Incomplete Types
It is possible to have an access type that points
to an object that has elements which are also
access types.

type type-name;

VISHAL MOYAL/VHDL 88
 Data Types

VISHAL MOYAL/VHDL 89
 Data Types
File Types
Objects of file types represent files in the
host environment.

They provide a mechanism by which a

VHDL design communicates with the host
environment.

VISHAL MOYAL/VHDL 90
 Data Types
type file-type-name is file of type-name,

The type-name is the type of values contained in

the file.

type VECTORS is file of BIT_VECTOR;

type NAMES is file of STRING;

VISHAL MOYAL/VHDL 91
 Data Types
A file is declared using a file declaration.

file file-name: file-type-name is mode

string-expression ,

VISHAL MOYAL/VHDL 92
 Operators
The predefined operators in the language are
classified into the following five categories:

1. Logical operators
2. Relational operators
3. Adding operators
4. Multiplying operators
5. Miscellaneous operators

VISHAL MOYAL/VHDL 93
 Operators
Logical Operators

and or nand nor xor not

Relational Operators

= /= < <= > >=

VISHAL MOYAL/VHDL 94
 Operators
Adding Operators
+ - &
'0' & '1'
results in an array of characters "01".

'C' & 'A' & 'T'

results in the value "CAT".

"BA" & "LL"

creates an array of characters "BALL.
VISHAL MOYAL/VHDL 95
 Operators
Multiplying Operators

* / mod rem

A rem B = A - ( A / B ) * B

A mod B = A B * N -For some integer N.

VISHAL MOYAL/VHDL 96
 Operators
Miscellaneous Operators

abs **

VISHAL MOYAL/VHDL 97