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Verilog A Language: Adapted From (The Designer'S Guide To VERILOG-AMS, Kenneth S. Kundert)

1. Verilog-A is a language for describing analog and mixed-signal systems through continuous-time modeling. It allows modeling of systems that process continuous-time signals. 2. A key application of Verilog-A is simulation, which applies stimuli to executable models to predict system behavior. Verilog-A modules describe individual components and how they are interconnected. 3. The resistor module models a linear resistor using a resistance parameter r. It relates the voltage across the resistor ports p and n to the current through those ports using Ohm's law.

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Ahmed Edris
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64 views14 pages

Verilog A Language: Adapted From (The Designer'S Guide To VERILOG-AMS, Kenneth S. Kundert)

1. Verilog-A is a language for describing analog and mixed-signal systems through continuous-time modeling. It allows modeling of systems that process continuous-time signals. 2. A key application of Verilog-A is simulation, which applies stimuli to executable models to predict system behavior. Verilog-A modules describe individual components and how they are interconnected. 3. The resistor module models a linear resistor using a resistance parameter r. It relates the voltage across the resistor ports p and n to the current through those ports using Ohm's law.

Uploaded by

Ahmed Edris
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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1

VERILOG A LANGUAGE
Ahmed Edris Adapted from (THE DESIGNERS GUIDE TO
2017 VERILOG-AMS, Kenneth S. Kundert)
2 INTRODUCTION
Hardware description languages
3
(HDLs)
Programming languages developed to describe
procedures that consist of a sequence of operations
performed in a serial manner to the data in
memory or on the CPU peripheral elements.
In typical hardware systems, there are many
individual components that all operate
simultaneously.
To properly describe hardware, one must be able
to describe both the behavior of the individual
components as well as how they are interconnected.
Hardware description languages
4
Applications
Simulation:
With simulation, one applies various stimuli to an
executable model that is described using the HDL in
order to predict how it will respond.

Simulationallows you to understand how complex


systems behave before you incur the time and expense
of implementing them.
Hardware description languages
5
Applications
Synthesis:
Synthesisis the process of actually implementing the
hardware.
Here the assumption is that the HDL is used to describe
the hardware at an abstract level using component
models that do not yet have a physical implementation,
and that synthesis is the act of creating a new refined
description with equivalent behavior at the inputs and
outputs that uses components that do have a physical
implementation
Hardware description languages
6
Applications
Simulation:
The goal for HDLs used for simulation is expressiveness:
they should be able to describe a wide variety of
behaviors easily.
Synthesis:
The goal for HDLs used for synthesis is realizability:
they should only allow those behaviors that can be
converted into an implementation to be described. As
such, if a single language is used for both simulation
and synthesis, then generally synthesis only supports a
relatively constrained subset of the language.
Hardware description languages
7
Applications
Currently only digital finite-state machines are
automatically synthesized. In this case, the desired
behavior is described at the register-transfer level
(RTL) using a well-defined subset of an HDL.
Synthesis then converts the RTL description to an
optimized gate-level description.
Automated synthesis of analog or mixed-signal
systems from a description of its desired behavior
has not progressed to the point where it is practical
except in a few very restricted cases.
Verilog A
8

Verilog-A is designed to allow modeling of systems


that process continuous-time signals. While it can
also handle systems that process the other types of
signals, it is not efficient for doing so.
Verilog-A is the analog subset of Verilog-AMS.
Verilog-A - Resistor
9

// Linear resistor (resistance formulation)


`include disciplines.vams
module resistor (p, n);
parameter real r=0; // resistance (Ohms)
inout p, n;
electrical p, n;
analog
V(p,n) <+ r* l(p,n);
endmodule
Verilog-A - Resistor
10

// Linear resistor (resistance formulation)

The // characters begin a comment , which extends


to the end of the line.
Comments can also be written inline by using /* to
start the comments, and */ to end them, enabling
multiline comments.
Verilog-A - Resistor
11

`include disciplines.vams

A collection of common disciplines and natures are


defined in a file disciplines.vams.
A discipline is a collection of related physical signal
types, which in Verilog-A/MS are referred to as
natures.
For example, the electrical discipline consists of
voltages and currents, where both voltage and
current are natures.
Verilog-A - Resistor
12

module resistor (p, n);

The basic building blocks of Verilog-A/MS are


modules.
Modules are descriptions of individual components.
In Verilog-A/MS modules are a block of statements
that begin with the keyword module, which is then
followed by the name of the module and the list of
ports. The statement is terminated with a semicolon.
Verilog-A - Resistor
13

parameter real r=0;

A parameter is specified for the module using the


parameter statement.
All parameters must be given default values
Specifying the type, in this case real, is optional. If
not given, the parameter will take the type of the
default value.
Verilog-A - Resistor
14

inout p, n;
electrical p, n;

A parameter is specified for the module using the


parameter statement.
All parameters must be given default values
Specifying the type, in this case real, is optional. If
not given, the parameter will take the type of the
default value.

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