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System-On-Chip Challenges in The Deep-Sub-Micron Era

The document discusses several challenges for system-on-chip (SoC) design in the deep-submicron era, including rising costs, complexity, power and reliability issues. It argues that approaches using higher abstraction levels and software are needed to effectively design systems with over 100 million transistors. New design methodologies are also needed to manage factors like leakage current, soft errors, and variability. Reliability will be a major roadblock requiring layered and platform-based design as well as online verification techniques. Mixed-signal and asynchronous timing strategies may also play important roles.

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Hemant Saraswat
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57 views17 pages

System-On-Chip Challenges in The Deep-Sub-Micron Era

The document discusses several challenges for system-on-chip (SoC) design in the deep-submicron era, including rising costs, complexity, power and reliability issues. It argues that approaches using higher abstraction levels and software are needed to effectively design systems with over 100 million transistors. New design methodologies are also needed to manage factors like leakage current, soft errors, and variability. Reliability will be a major roadblock requiring layered and platform-based design as well as online verification techniques. Mixed-signal and asynchronous timing strategies may also play important roles.

Uploaded by

Hemant Saraswat
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PPT, PDF, TXT or read online on Scribd
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System-on-chip Challenges in the

Deep-sub-micron Era
The Demise of ASIC
The Demise of ASIC cont. 1

Non-Recurring
Engineering (NRE)
cost of manufacturing Sub-micron design is approching
$1M for the 0.13 m CMOS
technology node;
predicted to between $2M and
$5M in 2 to 3 years from now;
ASIC starts suffer the most from
the trend;
Favor approaches where
customization achieved by software
or configurable hardware (ASSPs)

Cost of mask set versus technology node


The Demise of ASIC cont. 2

Deep-submicron effects
ASIC designer expose to indefinite number of problems;
Issues like interconnect delay,crosstalk and supply noise impact
the predictability of final design;
EDA vendors are struggling to solve timing closure and capacity
issues, in the attempt to extend the life of their tools.
Power dissipation, leakage, and variability compound the
problem.
Verification has come to dominate the overall design cost.
The Demise of ASIC cont. 3

Complexity
Design with more than 100 million transistors are not
exceptional anymore;
Complexity increase requires either large design team, or
raise the time-to-market;
Aggressive reuse of large modules and raise in abstraction
levels can help to address this challenging issues.
The SoC challenges
Managing and Exploiting Flexibility (i.e. Introducing
higher levels of abstraction)
Moving towards programmable solutions to save NRE and
design costs and reduce time-to-market.
This trend requires software as an essential component.
High level of abstraction consisting of mathematical model
of the functions.
This approach goes to the name model-based software
design;
Software for timing and power estimation, analysis,
synthesis, formal verification are all important components.
The SoC challenges (cont. 1)
Implementation techniques for a set of functions can be
approached with the same method at all levels of
abstraction;
Various levels in a seamless environment that is based on
the platform-based design.
The SoC challenges (cont. 2)
Power and Energy
Power and energy management and minimization have
been concern in CMOS for over more than a decade.
Power and energy management is emerging as one of the
most dominate roadblock because of
Integration complexity;
Side-effects of deep submicron transistor scaling.
soft error -An error occurrence in a computer's memory system that changes an
instruction in a program or a data value. Soft errors typically can be remedied by cold
booting the computer. A soft error will not damage a system's hardware; the only
damage is to the data that is being processed.

There are two types of soft errors:


chip-level soft error: These errors occur when the radioactive atoms in the chip's
material decay and release alpha particles into the chip. Because an alpha particle contains a
positive charge and kinetic energy, the particle can hit a memory cell and cause the cell to
change state to a different value. The atomic reaction is so tiny that it does not damage the
actual structure of the chip. Chip-level errors are rare because modern memory is so stable
that it would take a typical computer with a large memory capacity at least 10 years before
the radioactive elements of the chip's materials begin to decay.

system-level soft error: These errors occur when the data being processed is hit with a
noise phenomenon, typically when the data is on a data bus. The computer tries to interpret
the noise as a data bit, which can cause errors in addressing or processing program code.
The bad data bit can even be saved in memory and cause problems at a later time.
The SoC challenges (cont.3 )
New design approaches and accompanying design
methodologies are a necessity
Solutions to management of leakage and timing uncertainty for low-voltage
design;
Impact to reliability from soft errors and reduced signal-to-noise ratio;
Power and energy management is best addressed as a system-level problem;
ASSPs replace ASICs by speed demands for IC design.
Reliability and Robustness
Variety of factors are conspiring reduce the reliability of
integrated systems
Reduce signal-to-noise ratio by power considerations;
Soft errors by voltage scaling inject dynamic errors into computation;
Increased impact of process variations,quantum fluctuations, projected
proneness to errors of nano-technologies.
The SoC challenges (cont. 4)
The integration of multiple hybrid and mixed-signal
technologies on the same die further reduces the design
robustness, but can be addressed by
A layered top-down design as advocated in platform-based design is the
only way of dealing with dynamic errors;
Verification and test approaches are on a convergence(more than one
approchces) and substantial fractions turned into online activities.
The SoC challenges (cont. 5)
Predictability(degree of correctness) and Timing
Strategies
Timing predictability will continue to decline over the coming years;
This can be contributed to increased variations in both device
characteristics and interconnect parameters;
Uncertainty margin over clock period will increase;
The only solution is to step away from the worst-case (synchronous)
design by either:
Allowing occasional timing errors to occur- which trade off reliability;
By stepping away from the synchronous paradigm;
We predict that asynchronous (or other non-synchronous) timing
strategies will play an important role.
The SoC challenges (cont. 5)
Real-Time Emulation
A complete portfolio of complementary verification techniques
(including simulation,emulation,online checking, as well as
formal verification) and an overlaying methodology for their
development is necessary.
System level verification by availibility of complex heterogeneous field
programmable devices.
Engine constructed and rapid mapping make real-time emulation of
complex systems.
A fast prototyping path can go a long way in aiding the verification task
The SoC challenges (cont.
6)
Mixed Everything (Mixed-Signal & Mixed-Technology)
Integating multiple hybrid technologies into a single
component or package.
Not only digital computational functions
But also periphery and interfaces to the external world.

The tight integration of the components requires a design


methodology that considers them in concert.
Mixed-signal, mixed-technology methodologies, re-use
strategies and tool-sets are essential components of any SoC
development.
The SoC challenges (cont. 7)
Beyond Silicon
New technologies and devices (commonly dubbed nano-
technologies) are most likely to come into play
Platform-based design methodology(GSRC), based on a
stacked layer of abstractions, is universal and is well-suited to
encapsulate late-silicon and nano-technoloy devices and
fabrics.

* GSRC Gigascale Systems Research Center

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