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Computer Architecture: Mr. C. Ncube and Mrs. Marabada (Introduction To IT Laboratory)

The document discusses the Von Neumann architecture of computers. It describes the typical components of a computer based on this architecture including the memory, control unit, arithmetic logic unit, and input/output. It then provides more details on topics like the central processing unit, different types of processors and their specifications over time, memory hierarchies and technologies, virtual memory management, and buffers.

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Clemence Munaki
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42 views

Computer Architecture: Mr. C. Ncube and Mrs. Marabada (Introduction To IT Laboratory)

The document discusses the Von Neumann architecture of computers. It describes the typical components of a computer based on this architecture including the memory, control unit, arithmetic logic unit, and input/output. It then provides more details on topics like the central processing unit, different types of processors and their specifications over time, memory hierarchies and technologies, virtual memory management, and buffers.

Uploaded by

Clemence Munaki
Copyright
© © All Rights Reserved
Available Formats
Download as PPT, PDF, TXT or read online on Scribd
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Computer Architecture

Mr. C. Ncube and Mrs. Marabada


(Introduction to IT Laboratory)

1
The Von Neumann Architecture
An abstract view of a computer
Due to John Von Neumann (Hungarian
mathematician) 1945 paper Von Neumann
Computer consists of:
Memory
Control Unit
Arithmetic Logic Unit
Image from: http://www.llnl.gov/computing/tutorials/parallel_com
Input/Output
Data and instructions reside in memory
Instructions are fetched from memory and
executed in the CPU
Instructions may cause data to be fetched from
memory and operated upon (for example: C =
A+B)

2
Von Neumann Architecture
More Details

Image from:http://www.cise.ufl.edu/~mssz/CompOrg/Figure1.8-vonNeumannArch.gif

3
Inside a Personal Computer

Image from: http://www.martincomputing.com/hardware.htm

4
A Mother Board
1. Mouse & keyboard
2. USB
3. Parallel port
4. CPU Chip
5. RAM slots
6. Floppy controller
7. IDE controller
8. PCI slot
9. ISA slot
10. CMOS Battery
11. AGP slot
12. CPU slot
13. Power supply plug in

Image from: http://www.martincomputing.com/hardware.htm

5
PCI Bus (Peripheral
Component Interconnect)

Image from: http://biology.ncsa.uiuc.edu/.

6
CPU
Comprises:
A Data Path to carry out the operations
(Arithmetic-Logic Unit)
A Control Unit that controls all the operations
performed and the flow of data to/from the
various operating units (adders, multipliers, etc.)
Often denoted by:
The width of ALU (32, 64 bits)
The speed of the clock (GHz)

7
Intel Processor Comparison
Clock
Name Date Transistors Microns Data width MIPS
speed
8080 1974 6,000 6 2 MHz 8 bits 0.64
16 bits
8088 1979 29,000 3 5 MHz 8-bit 0.33
bus

80286 1982 134,000 1.5 6 MHz 16 bits 1

80386 1985 275,000 1.5 16 MHz 32 bits 5

80486 1989 1,200,000 1 25 MHz 32 bits 20


32 bits
Pentium 1993 3,100,000 0.8 60 MHz 64-bit 100
bus
32 bits
Pentium II 1997 7,500,000 0.35 233 MHz 64-bit ~300
bus
32 bits
Pentium III 1999 9,500,000 0.25 450 MHz 64-bit ~510
bus
32 bits
Pentium 4 2000 42,000,000 0.18 1.5 GHz 64-bit ~1,700
Table from: http://computer.howstuffworks.com/microprocessor2.htm
bus
Pentium 4 Fall bimester 2006 32 bits
125,000,00
"Presc 2004 0.09 3.6 GHz 64-bit ~7,000
Pentium 4 and Memory speeds
In theory, a pentium4 can operate at about
1700 MIPS = 1.7 x 109 instr/s
An instruction like C = A+B requires:
One fetch from memory for the instruction
Two fetches from memory for the operands A, B
One store to memory for the result C
Total: about 1.7 x 4 x 109 = 6.8 x 109
accesses/s
RAM should be accessible in 1s/ 6.8 x 109 =
0.147 ns
But SDRAMs have access times of the order of 15 ns!
9
Overcoming the CPU and RAM
Speed Difference

Bring in data on wider bus (for example


2 successive instructions each time)
Use (small) fast cache memory in the
CPU and move larger chunks of data
to/from memory
Use a fast cache for instructions
Current CPUs have a small/fast inner cache (L1) and have a
secondary bigger/slower cache (L2).
If the data/instruction required is not in L1 or in L2, it must be
(slowly) fetched from RAM
10
Other Processors
Tasks to be performed:
Run the operating system and the application software
Pay attention to various peripherals
Update graphics on screen

Some of these tasks can be demanded from other
additional processors such as:
Graphic processor
Network card
Disc/bus controllers
(Memory management unit MMU)
(Floating Point Unit FPU)

11
Co-processors and
Multi-processors

Co-processors: Under the control of the


CPU perform specific tasks CPU
RAM

Coprocessor

Multi-processors: Multiple independent


CPUs that share some CPU 1

resources and operate RAM

in parallel on different tasks CPU 2

12
Memories
ROM: Read only memory cannot be
changed non volatile
EPROM: Electrically Programmable ROM
Like ROM, but can be changed
(upgrade of the firmware)
RAM: Random Access memory - the
core memory of the computer

13
Various RAMs
DRAM: dynamic RAM the most common
memory of a computer
Volatile! All information contained lost when
power switched off
Contents degrade with time
Needs to be refreshed every few milliseconds
SRAM: Static RAM fast, non-volatile,
expensive, power hungry used in caches

14
Various DRAMs
FPM: Fast Page Mode
} OLD
EDO: Extended Data Out
SDRAM: Synchronous DRAM can be
synchronized with the CPU clock
DDR DRAM: Double Data Rate DRAM like
SDRAM but moves data at twice the speed
RDRAM: Rambus DRAM designed for the
Intel Pentium Not very popular

15
Virtual Memory
Programs/data can be
executed/processed only when they are
in main memory (RAM)
Manage memory so that it appears that
the accessible main memory is larger
than the physical RAM available
Use a portion of the hard disc as if it
were main memory (swap area)

16
Managing Virtual Memory
Pages will be moved in/out of swap area as
needed
What pages should be kept in (fast) RAM?
Which should be moved to (slow) disc?
Page replacement algorithms:
Random
FIFO
LRU
An unfortunate choice of page replacements
can result in VERY SLOW operation - thrashing
17
Memory Hierarchy
CPU registers
L1 (L2, L3) cache
DRAM
Hard disc

18
Memory Buffers
Buffers: memory areas set aside to provide
temporary storage for data streams
They can be used to:
Provide some flexibility in the times required by a
producer and a consumer of a data stream (disc,
keyboard, , different processes, )
Permit cut-paste of data between different
applications

19

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