UART and USART

UART
stands for Universal Asynchronous Receiver/Transmitter. From the name itself, it is clear that it
is asynchronous i.e. the data bits are not synchronized with the clock pulses.

USART
stands for Universal Synchronous Asynchronous Receiver/Transmitter. This is of the
synchronous type, i.e. the data bits are synchronized with the clock pulses.

If you refer to the USART section in the datasheet of any AVR microcontroller, you will find
several features listed there. Some of the main features of the AVR USART are:

Full Duplex Operation (Independent Serial Receive and Transmit Registers)

Asynchronous or Synchronous Operation
Master or Slave Clocked Synchronous Operation
High Resolution Baud Rate Generator
Supports Serial Frames with 5, 6, 7, 8, or 9 Data bits and 1 or 2 Stop Bit
 USART Layout How to set it up?
Before we continue, please note that the AVR USART is fully
compatible with the AVR UART in terms of register bit locations,
baud rate generation, transmitter/receiver operations and buffer
functionality. So let us now have a quick look at how to set up
USART in general. We will discuss in detail later.
The first step is to set the baud rate in both, the master and the
slave. The baud rate has to be the same for both master and
slave.
Set the number of data bits, which needs to be sent.
Get the buffer ready! In case of transmission (from AVR to some
other device), load it up with the data to be sent, whereas in case
of reception, save the previous data so that the new received data
can be overwritten onto it.
Then enable the transmitter/receiver according to the desired
usage.
 One thing to be noted is that in UART, there is no
master or slave since master is defined by the
MicroController, which is responsible for clock pulse
generation. Hence Master and Slave terms occur only
in the case of USART.
Master C is the one which is responsible for Clock
pulse generation on the Bus.
 USART Pin Configuration
Now lets have a look at the hardware pins related to USART.
The USART of the AVR occupies three hardware pins pins:

RxD: USART Receiver Pin (ATMega8 Pin 2; ATMega16/32 Pin 14)

TxD: USART Transmit Pin (ATMega8 Pin 3; ATMega16/32 Pin 15)
XCK: USART Clock Pin (ATMega8 Pin 6; ATMega16/32 Pin 1)
 Modes of Operation
The USART of the AVR can be operated in three
modes, namely-
Asynchronous Normal Mode
Asynchronous Double Speed Mode
Synchronous Mode
 Asynchronous Normal Mode
In this mode of communication, the data is
transmitted/received asynchronously, i.e. we
do not need (and use) the clock pulses, as well
as the XCK pin. The data is transferred at the
BAUD rate we set in the UBBR register. This is
similar to the UART operation.
Asynchronous Double Speed Mode
This is higher speed mode for asynchronous communication. In this
mode also we set the baud rates and other initializations similar to
Normal Mode. The difference is that data is transferred at double
the baud we set in the UBBR Register.

Setting the U2X bit in UCSRA register can double the transfer rate.
Setting this bit has effect only for the asynchronous operation. Set
this bit to zero when using synchronous operation. Setting this bit
will reduce the divisor of the baud rate divider from 16 to 8,
effectively doubling the transfer rate for asynchronous
communication. Note however that the Receiver will in this case
only use half the number of samples (reduced from 16 to 8) for
data sampling and clock recovery, and therefore a more accurate
baud rate setting and system clock are required when this mode is
used. For the Transmitter, there are no downsides.
 Synchronous Mode
This is the USART operation of AVR. When
Synchronous Mode is used (UMSEL = 1 in
UCSRC register), the XCK pin will be used as
either clock input (Slave) or clock output
(Master).
 Baud Rate Generation
The baud rate is the rate at which information is transferred in a
communication channel. In the serial port context, "9600 baud" means
that the serial port is capable of transferring a maximum of 9600 bits per
second.
The baud rate of UART/USART is set using the 16-bit wide UBRR register.
The register is as follows:
 Since AVR is an 8-bit microcontroller, every register should
have a size of 8 bits. Hence, in this case, the 16-bit UBRR
register is comprised of two 8-bit registers UBRRH (high) and
UBRRL (low). This is similar to the 16-bit ADC register (ADCH
and ADCL, remember?). Since there can be only specific baud
rate values, there can be specific values for UBRR, which when
converted to binary will not exceed 12 bits. Hence there are
only 12 bits reserved for UBRR[11:0]. We will learn how to
calculate the value of UBRR in a short while in this post.
 The USART Baud Rate Register (UBRR) and the down-
counter connected to it functions as a programmable
prescaler or baud rate generator. The down-counter,
running at system clock (FOSC), is loaded with the UBRR
value each time the counter has counted down to zero
or when the UBRRL Register is written. A clock is
generated each time the counter reaches zero.
This clock is the baud rate generator clock output (=
FOSC/(UBRR+1)). The transmitter divides the baud rate
generator clock output by 2, 8, or 16 depending on
mode. The baud rate generator output is used directly
by the receivers clock and data recovery units.
 BAUD = Baud Rate in Bits/Second (bps) (Always remember, Bps =
Bytes/Second, whereas bps = Bits/Second)
FOSC = System Clock Frequency (1MHz) (or as per use in case of
external oscillator)
UBRR = Contents of UBRRL and UBRRH registers
 Frame Formats
A frame refers to the entire data packet which is being
sent/received during a communication. Depending upon the
communication protocol, the formats of the frame might vary.
For example, TCP/IP has a particular frame format, whereas
UDP has another frame format. Similarly in our case, RS232
has a typical frame format as well
A typical frame for USART/RS232 is usually 10 bits long: 1 start
bit, 8 data bits, and a stop bit. However a vast number of
configurations are available 30 to be precise!
Order of Bits
Start bit (Always low)
Data bits (LSB to MSB) (5-9 bits)
Parity bit (optional) (Can be odd or even)
Stop bit (1 or 2) (Always high)
A frame starts with the start bit followed by the least significant data bit. Then the next data
bits, up to a total of nine, are succeeding, ending with the most significant bit. If enabled, the
parity bit is inserted after the data bits, before the stop bits. When a complete frame is
transmitted, a new frame can directly follow it, or the communication line can be set to an
idle (high) state. Here is the frame format as mentioned in the AVR datasheet-
 Setting Number of STOP Bits
This bit selects the number of stop bits to be inserted by
the transmitter. The Receiver ignores this setting. The USBS
bit is available in the UCSRC Register.
 Register Description
Now lets learn about the registers which deal with the USART.
If you have worked with ADC and timers before, you would
know that we need to program the registers in order to make
the peripheral work. The same is the case with USART. The
USART of AVR has five registers, namely UDR, UCSRA, UCSRB,
UCSRC and UBBR. We have already discussed about UBBR
earlier in this post, but we will have another look.
 UDR: USART Data Register (16-bit)
The USART Transmit Data Buffer Register and USART Receive Data Buffer Registers
share the same I/O address referred to as USART Data Register or UDR. The
Transmit Data Buffer Register (TXB) will be the destination for data written to the
UDR Register location. Reading the UDR Register location will return the contents
of the Receive Data Buffer Register (RXB).
For 5-, 6-, or 7-bit characters the upper unused bits will be ignored by the
Transmitter and set to zero by the Receiver.
 UCSRA: USART Control and Status
Register A (8-bit)

Bit 7: RxC USART Receive Complete Flag: This flag bit is set by the CPU when
there are unread data in the Receive buffer and is cleared by the CPU when the
receive buffer is empty. This can also be used to generate a Receive Complete
Interrupt (see description of the RXCIE bit in UCSRB register).
Bit 6: TxC USART Transmit Complete Flag: This flag bit is set by the CPU when
the entire frame in the Transmit Shift Register has been shifted out and there is no
new data currently present in the transmit buffer (UDR). The TXC Flag bit is
automatically cleared when a Transmit Complete Interrupt is executed, or it can be
cleared by writing a one (yes, one and NOT zero) to its bit location. The TXC Flag
can generate a Transmit Complete Interrupt (see description of the TXCIE bit in
UCSRB register).
 Bit 5: UDRE USART Data Register Empty: The UDRE Flag
indicates if the transmit buffer (UDR) is ready to receive
new data. If UDRE is one, the buffer is empty, and therefore
ready to be written. The UDRE Flag can generate a
Data Register Empty Interrupt (see description of the UDRIE
bit in UCSRB register). UDRE is set after a reset to indicate
that the Transmitter is ready.
Bit 4: FE Frame Error: This bit is set if the next character
in the receive buffer had a Frame Error when received (i.e.
when the first stop bit of the next character in the receive
buffer is zero). This bit is valid until the receive buffer (UDR)
is read. The FE bit is zero when the stop bit of received data
is one. Always set this bit to zero when writing to UCSRA.
 Bit 3: DOR Data Overrun Error: This bit is set if a Data
OverRun condition is detected. A Data OverRun occurs
when the receive buffer is full (two characters), and a
new start bit is detected. This bit is valid until the
receive buffer (UDR) is read. Always set this bit to zero
when writing to UCSRA.
Bit 2: PE Parity Error: This bit is set if the next
character in the receive buffer had a Parity Error when
received and the parity checking was enabled at that
point (UPM1 = 1). This bit is valid until the receive
buffer (UDR) is read. Always set this bit to zero when
writing to UCSRA.
 Bit 1: U2X Double Transmission Speed: This bit only has effect for
the asynchronous operation. Write this bit to zero when using
synchronous operation. Writing this bit to one will reduce the
divisor of the baud rate divider from 16 to 8 effectively doubling the
transfer rate for asynchronous communication.
Bit 0: MPCM Multi-Processor Communication Mode: This bit
enables the Multi-processor Communication mode. When the
MPCM bit is written to one, all the incoming frames received by the
USART Receiver that do not contain address information will be
ignored. The Transmitter is unaffected by the MPCM setting. This is
essential when the receiver is exposed to more than one
transmitter, and hence must use the address information to extract
the correct information.
 UCSRB: USART Control and Status
Register B (8-bit)

Bit 7: RXCIE RX Complete Interrupt Enable: Writing this bit to one

enables interrupt on the RXC Flag. A USART Receive Complete interrupt
will be generated only if the RXCIE bit is written to one, the Global
Interrupt Flag in SREG is written to one and the RXC bit in UCSRA is set.
The result is that whenever any data is received, an interrupt will be fired
by the CPU.
Bit 6: TXCIE TX Complete Interrupt Enable: Writing this bit to one
enables interrupt on the TXC Flag. A USART Transmit Complete interrupt
will be generated only if the TXCIE bit is written to one, the Global
Interrupt Flag in SREG is written to one and the TXC bit in UCSRA is set.
The result is that whenever any data is sent, an interrupt will be fired by
the CPU.
 Bit 5: UDRIE USART Data Register Empty Interrupt
Enable: Writing this bit to one enables interrupt on the UDRE Flag
(remember bit 5 in UCSRA?). A Data Register Empty interrupt will
be generated only if the UDRIE bit is written to one, the Global
Interrupt Flag in SREG is written to one and the UDRE bit in UCSRA
is set. The result is that whenever the transmit buffer is empty, an
interrupt will be fired by the CPU.
Bit 4: RXEN Receiver Enable: Writing this bit to one enables the
USART Receiver. The Receiver will override normal port operation
for the RxD pin when enabled.
Bit 3: TXEN Transmitter Enable: Writing this bit to one enables
the USART Transmitter. The Transmitter will override normal port
operation for the TxD pin when enabled.
 Bit 2: UCSZ2 Character Size: The UCSZ2 bits combined
with the UCSZ1:0 bits in UCSRC register sets the number of
data bits (Character Size) in a frame the Receiver and
Transmitter use. More information given along with
UCSZ1:0 bits in UCSRC register.
Bit 1: RXB8 Receive Data Bit 8: RXB8 is the ninth data bit
of the received character when operating with serial frames
with nine data bits. It must be read before reading the low
bits from UDR.
Bit 0: TXB8 Transmit Data Bit 8: TXB8 is the ninth data bit
in the character to be transmitted when operating with
serial frames with nine data bits. It must be written before
writing the low bits to UDR.
 UCSRC: USART Control and Status
Register C (8-bit)
The UCSRC register can be used as either
UCSRC, or as UBRRH register. This is done
using the URSEL bit.

Bit 7: URSEL USART Register Select: This bit selects between accessing the UCSRC
or the UBRRH Register. It is read as one when reading UCSRC. The URSEL must be
one when writing the UCSRC.
Bit 6: UMSEL USART Mode Select: This bit selects between Asynchronous and
Synchronous mode of operation.
 Bit 5:4: UPM1:0 Parity Mode: This bit helps you
enable/disable/choose the type of parity.

Bit 3: USBS Stop Bit Select: This bit helps you choose the number of stop bits for
your frame.
 Bit 2:1: UCSZ1:0 Character Size: These two bits in combination with the UCSZ2
bit in UCSRB register helps choosing the number of data bits in your frame.

Bit 0: UCPOL Clock Polarity: This bit is used for Synchronous mode only. Write this bit to
zero when Asynchronous mode is used. The UCPOL bit sets the relationship between data
output change and data input sample, and the synchronous clock (XCK).
 Lets code it!

Now its been enough of theory. Lets get our hands dirty with some
actual code! Here is how we will structure out code first initialize
UART, then read from it, and then write to it.
Initializing UART
Initializing UART involves the following steps:
Setting the Baud Rate
Setting Data Size (5/6/7/8/9 bits)
Enabling Reception/ Transmission (In the TXEN and RXEN bits in
UCSRB)
Setting parity, and number of Stop Bits.
Below is the code to initialize UART, explanation follows it. You can
scroll the code sideways in order to view it completely.
// define some macros
#define BAUD 9600 // define baud
#define BAUDRATE ((F_CPU)/(BAUD*16UL)-1) // set baud rate value for
UBRR

// function to initialize UART

void uart_init (void)
{
UBRRH = (BAUDRATE>>8); // shift the register right by 8 bits
UBRRL = BAUDRATE; // set baud rate
UCSRB|= (1<<TXEN)|(1<<RXEN); // enable receiver and transmitter
UCSRC|= (1<<URSEL)|(1<<UCSZ0)|(1<<UCSZ1); // 8bit data format
}
 Explanation

The variable (or macro) used to set the baud rate is BAUD. The
variable (or macro) BAUDRATE is defined as per the calculations
according to which, the baud rate is set in the registers.
One thing to note is that UCSRC and UBRRH share the same I/O
location in the memory. So, the bit that controls the
selection/switching of the registers is the URSEL Bit in
the UCSRC register. This creates a lot of confusion, and if this bit is
not handled properly, UART doesnt work! So pay attention to the
code initialization.
If URSEL is zero during a write operation, the UBRRH value will be
updated. If URSEL is one, the UCSRC setting will be updated. This
means that while URSELbit is 0, and even if we are
addressing UCSRC, UBBRH will be addressed, which would in turn
result in setting up of wrong, non standard baud rates, and
everything getting messed up! Since the default value of URSEL is 0,
it is safe to first use UBRRH, and then use the UCSRC Register
 The bits TxEN and RxEN are set to 1 to enable
UART transmission and reception.
The Bits UCSZ0 and UCSZ1 are used to select the
number of data bits to be transmitted. As per the
table, we have set the two bits to
transmit/receive 8 bits.
 Transmission/Reception Code

The following code is for transmitting data, explanation

follows it. You can scroll the code sideways in order to
view to code completely.
/ function to send data
void uart_transmit (unsigned char data)
{
while (!( UCSRA & (1<<UDRE))); // wait while register is free
UDR = data; // load data in the register
}
 The following code is for transmitting data, explanation
follows it. You can scroll the code sideways in order to
view to code completely.
// function to receive data
unsigned char uart_recieve (void)
{
while(!(UCSRA) & (1<<RXC)); // wait while
data is being received
return UDR; // return 8-bit data
}
 Explanation
The above code snippets are to transmit and receive
data respectively. In both of them, we first wait for the
flag bits denoting data register empty bit UDRE, and
receive complete RXC bit respectively to get set, and
then take the next action.
When we transmit the data, we load the 8-bit data into
the UDR (UART Data Register) to be transmitted.
When we want to receive data, we wait for the whole
data to be received first, and then return the value of
the received data stored in UDR.