Computer Architecture

Lecture 1: Introduction and

Basics
Question: What Is This?

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Answer: Masterpiece of A Famous
Architect

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But First.
Find The Differences Of This and That

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Find Differences Of This and
That

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A Key Question
How Was Wright Able To Design Fallingwater?
Can have many guesses
(Ultra) hard work, perseverance, dedication (over decades)
Experience of decades
Creativity
Out-of-the-box thinking
Principled design
A good understanding of past designs
Good judgment and intuition
Strong combination of skills (math, architecture, art, )

(You will be exposed to and hopefully develop/enhance

many of these skills in this course)

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A Quote from The Architect
Himself
architecture [] based upon principle, and not
upon precedent

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A Principled Design

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A Quote from The Architect
Himself
architecture [] based upon principle, and not
upon precedent

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Role of The (Computer)
Architect
Look backward (to the past)
Understand tradeoffs and designs, upsides/downsides, past
workloads. Analyze and evaluate the past.
Look forward (to the future)
Be the dreamer and create new designs. Listen to dreamers.
Push the state of the art. Evaluate new design choices.
Look up (towards problems in the computing stack)
Understand important problems and their nature.
Develop architectures and ideas to solve important problems.
Look down (towards device/circuit technology)
Understand the capabilities of the underlying technology.
Predict and adapt to the future of technology (you are
designing for N years ahead). Enable the future technology.

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Takeaways
Being an architect is not easy
You need to consider many things in designing a new
system + have good intuition/insight into ideas/tradeoffs

But, it is fun and can be very technically rewarding

And, enables a great future
E.g., many scientific and everyday-life innovations would
not have been possible without architectural innovation that
enabled very high performance systems
E.g., your mobile phones

This course will teach you how to become a good

computer architect

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So, I Hope You Are Here for
This C as a model of computation
Programmers view of how
a computer system works

Architect/microarchitects view:
What How to design a computer that
happens in- meets system design goals.
between? Choices critically affect both
the SW programmer and
the HW designer

HW designers view of how

a computer system works
Digital logic as a
model of computation
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Levels of Transformation
The purpose of computing is insight (Richard Hamming)
We gain and generate insight by solving problems
How do we ensure problems are solved by electrons?

Problem
Algorithm
Program/Language
Runtime System
(VM, OS, MM)
ISA (Architecture)
Microarchitecture
Logic
Circuits
Electrons

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The Power of Abstraction
Levels of transformation create abstractions
Abstraction: A higher level only needs to know about the
interface to the lower level, not how the lower level is
implemented
E.g., high-level language programmer does not really need to
know what the ISA is and how a computer executes
instructions

Abstraction improves productivity

No need to worry about decisions made in underlying levels
E.g., programming in Java vs. C vs. assembly vs. binary vs.
by specifying control signals of each transistor every cycle

Then, why would you want to know what goes on

underneath or above?

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Crossing the Abstraction Layers
As long as everything goes well, not knowing what happens
in the underlying level (or above) is not a problem.

What if
The program you wrote is running slow?
The program you wrote does not run correctly?
The program you wrote consumes too much energy?

What if
The hardware you designed is too hard to program?
The hardware you designed is too slow because it does not provide the
right primitives to the software?

What if
You want to design a much more efficient and higher performance
system?

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Crossing the Abstraction Layers
Two key goals of this course are

to understand how a processor works underneath the

software layer and how decisions made in hardware
affect the software/programmer

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 An Example: Multi-Core
Systems
Multi-Core
Chip

L2 CACHE 1
L2 CACHE 0
SHARED L3 CACHE

DRAM INTERFACE
CORE 0

DRAM BANKS
CORE 1

DRAM MEMORY
CONTROLLER
L2 CACHE 2

L2 CACHE 3

CORE 2 CORE 3

*Die photo credit: AMD Barcelona

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Unexpected Slowdowns in
High priority
Multi-Core

Memory Performance Hog

Low priority

(Core 0) (Core 1)
Moscibroda and Mutlu, Memory performance attacks: Denial of memory se
in multi-core systems, USENIX Security 2007.
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A Question or Two
Can you figure out why there is a disparity in
slowdowns if you do not know how the system
executes the programs?

Can you fix the problem without knowing what is

happening underneath?

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Why the Disparity in
Slowdowns?
CORE
matlab1 gcc 2
CORE Multi-Core
Chip

L2 L2
CACHE CACHE
unfairness
INTERCONNECT
Shared DRAM
DRAM MEMORY CONTROLLER Memory System

DRAM DRAM DRAM DRAM

Bank 0 Bank 1 Bank 2 Bank 3

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DRAM Bank Operation
Access Address:
(Row 0, Column 0) Columns
(Row 0, Column 1)
(Row 0, Column 85)

Row decoder
(Row 1, Column 0)

Rows
Row address 0
1

Row 01
Row
Empty Row Buffer CONFLICT
HIT !

Column address 0
1
85 Column mux

Data

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DRAM Controllers
A row-conflict memory access takes significantly
longer than a row-hit access

Current controllers take advantage of the row buffer

Commonly used scheduling policy (FR-FCFS) [Rixner

2000]*
(1) Row-hit first: Service row-hit memory accesses first
(2) Oldest-first: Then service older accesses first

This scheduling policy aims to maximize DRAM

throughput
*Rixner et al., Memory Access Scheduling, ISCA 2000.
*Zuravleff and Robinson, Controller for a synchronous DRAM , US Patent 5,630,096, May 1997.

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The Problem
Multiple applications share the DRAM controller
DRAM controllers designed to maximize DRAM data
throughput

DRAM scheduling policies are unfair to some

applications
Row-hit first: unfairly prioritizes apps with high row buffer
locality
Threads that keep on accessing the same row
Oldest-first: unfairly prioritizes memory-intensive applications

DRAM controller vulnerable to denial of service attacks

Can write programs to exploit unfairness

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A Memory Performance Hog
// initialize large arrays A, B // initialize large arrays A, B

for (j=0; j<N; j++) { for (j=0; j<N; j++) {

index = j*linesize; streaming index = rand(); random
A[index] = B[index]; A[index] = B[index];

} }

STREAM RANDOM
- Sequential memory access - Random memory access
- Very high row buffer locality (96% hit rate) - Very low row buffer locality (3% hit rate)
- Memory intensive - Similarly memory intensive

Moscibroda and Mutlu, Memory Performance Attacks, USENIX Security 2

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What Does the Memory Hog
Do?

Row decoder
T0: Row 0
T0:
T1: Row 05
T1:
T0:Row
Row111
0
T1:
T0:Row
Row16
0
Memory Request Buffer Row
Row 00 Row Buffer

Row size: 8KB, cache blockColumn mux

size: 64B
T0: STREAM
128
T1: (8KB/64B)
RANDOM requests of T0 serviced
Data before T1

Moscibroda and Mutlu, Memory Performance Attacks, USENIX Security 2

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Now That We Know What Happens
Underneath
How would you solve the problem?

What is the right place to solve the problem?

Programmer?
Problem
System software? Algorithm
Compiler? Program/Language
Hardware (Memory controller)? Runtime System
Hardware (DRAM)? (VM, OS, MM)
Circuits? ISA (Architecture)
Microarchitecture
Two other goals of this course: Logic
Enable you to think critically Circuits
Enable you to think broadly Electrons

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What Will You Learn
Computer Architecture: The science and art of
designing, selecting, and interconnecting hardware
components and designing the hardware/software
interface to create a computing system that meets
functional, performance, energy consumption, cost,
and other specific goals.

Traditional definition: The term architecture is

used here to describe the attributes of a system as
seen by the programmer, i.e., the conceptual
structure and functional behavior as distinct from the
organization of the dataflow and controls, the logic
design, and the physical implementation. Gene
Amdahl, IBM Journal of R&D, April 1964

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