Chap.

12 Memory Organization 12-1

12-1 Memory Hierarchy

Memory hierarchy in a computer system : Fig. 12-1
Main Memory : memory unit that communicates directly with the CPU (RAM)
Auxiliary Memory : device that provide backup storage (Disk Drives)
Cache Memory : special very-high-speed memory to increase the processing speed
(Cache RAM)
A u x ilia r y m e m o r y
M a g n e tic
ta p e s
M a in
I/O p ro c e s s o r
m e m o ry
M a g n e tic
d is k s

C ache
CPU
m e m o ry

Multiprogramming
enable the CPU to process a number of independent program concurrently
Memory Management System : sec. 12-7
supervise the flow of information between auxiliary memory and main memory

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12-2 Main Memory

Bootstrap Loader
A program whose function is to start the computer software operating when power
is turned on P o w e r- O N

RAM and ROM Chips F F F F :0 0 0 0

( R e s e t P o in t)
Typical RAM chip : Fig. 12-2
128 X 8 RAM : 27 = 128 (7 bit address lines) P O ST
Bootstrap Loader
Typical ROM chip : Fig. 12-3 S y s te m In it. Bootstrap ROM
512 X 8 ROM : 29 = 512 (9 bit address lines) IN T 1 9 Boot ROM
C h ip s e le c t 1 CS1
L o a d B o o ts tra p R e c o rd
C h ip s e le c t 2 CS2 ( T ra c k 0 , S e c to r 0 )
128 8
Read RD 8 b it d a ta b u s
RAM
L o a d O p e r a tin g S y s te m
W r ite W R ( IO .S Y S , M S D O S .S Y S , C O M M A N D .C O M )
7 b it a d d r e s s AD7

( a ) B lo c k d ia g r a m C h i p s e le c t 1 CS1

CS1 CS2 RD W R M e m o r y f u n c tio n S ta te o f d a ta b u s C h i p s e le c t 2 CS2

0 0 In h ib it H ig h - im p e d a n c e
512 8
8 b it d a ta b u s
0 1 In h ib it H ig h - im p e d a n c e ROM
1 0 0 0 In h ib it H ig h - im p e d a n c e
1 0 0 1 W r ite In p u t d a ta to R A M
1 0 1 Read O u tp u t d a ta f ro m R A M 9 b it a d d r e s s AD9
1 1 In h ib it H ig h - im p e d a n c e

( b ) F u n c tio n ta b le

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Memory Address Map

Memory Configuration : 512 bytes RAM + 512 bytes ROM
1 x 512 byte ROM + 4 x 128 bytes RAM
Memory Address Map : Tab. 12-1 A d d re s s b u s CPU

16 - 11 10 9 8 7 - 1 RD W R D a ta b u s

Address line 9 8
D ecoder

RAM 1 0 0 : 0000 - 007F 3 2 1 0

C S1

RAM 1 0 1 : 0080 - 00FF C S2

RD
128 8 D a ta
RAM 1
RAM 1 1 0 : 0100 - 017F W R
AD7

RAM 1 1 1 : 0180 - 01FF C S1

Address line 10
C S2
128 8 D a ta
RD
RAM 2
W R
ROM 1 : 0200 - 03FF AD7

Memory Connection to CPU : Fig. 12-4 C S1

C S2
128 8 D a ta

2 x 4 Decoder : RAM select (CS1)

RD
RAM 3
W R
AD7

Address line 10 C S1

RAM select : CS2 C S2

RD
128 8 D a ta
RAM 4
ROM select : CS2 Invert W R
AD7

C S1
C S2
RD : ROM CS1 1- 7 128 8
RO M
D a ta
8

OE(Output Enable)
AD 9
9

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T ra c k s

12-3 Auxiliary Memory

Magnetic Disk : Fig. 12-5, FDD, HDD
Magnetic Tape : Backup or Program
Optical Disk : CDR, ODD, DVD te x t

12-4 Associative Memory

Content Addressable Memory (CAM)
R e a d /W r ite
A memory unit accessed by content head

Block Diagram : Fig. 12-6

A rg u m e n t r e g is te r ( A )

K e y re g is te r ( K )

A Register 101 111100 Argument

M a tc h
K Register 111 000000 Key (Mask) r e g is te r

Memory In p u t

Word 1 100 111100 M = 0 A s s o c ia tiv e m e m o r y

a r r a y a n d lo g ic M

Word 2 101 000011 M = 1 Match Logic

Read
m w o rd s
W r ite
n b its p e r w o r d

M = 1 O u tp u t

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m word x n cells per word : Fig. 12-7

A i K j

In p u t
A 1 A j A n

W rite
K 1 K j K n

W o rd 1 C 11 C 1j C 1n M 1 R S M a tc h
To M i
F ij lo g ic
Read
W o rd i C i1 C ij C in M i

W o rd m C m 1 C m j C m n M m

B it 1 B it j B it n

O u tp u t

Match Logic
One cell of associative memory : Fig. 12-8
Input = 1 or 0 Write F/F
A K Match Logic M=1 (M READ )
Read F/F

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Match Logic : Fig. 12-9 K 1 A 1 K 2 A 2 K n A n

Aj = Argument, Fij = Cell ij bit F 'i1 F i1 F 'i2 F i2 F 'in F in

j 1 bit match
xj = Aj Fij (1 AND 1)+ Aj Fij (0 AND 0)
1 - n n bits match Mi = x1x2..xn
Key bit Kj : xj + Kj
Kj = 0 : Aj Fij no comparison ( Kj : xj + 1 = 1 )
Kj = 1 : Aj Fij comparison ( Kj : xj + 0 = xj )
Match Logic for word I : M i

Mi = (x1 + K1) (x2 + K2). (xn + Kn)

n

= j 1
n
(xj + Kj)

= j 1
(Aj Fij + Aj Fij + Kj)

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12-5 Cache Memory

Locality of Reference
the references to memory tend to be confined within a few localized areas in
memory
Cache Memory : a fast small memory
keeping the most frequently accessed instructions and data in the fast cache
memory
Cache
cache size : 256 K byte ( 512 K byte)
mapping method : 1) associative, 2) direct, 3) set-associative
replace algorithm : 1) LRU, 2) LFU, 3) FIFO
write policy : 1) write-through, 2) write-back
Hit Ratio
the ratio of the number of hits divided by the total CPU references (hits + misses) to
memory
hit : the CPU finds the word in the cache ( 0.9 )
miss : the word is not found in cache (CPU must read main memory)
: cache memory access time = 100 ns, main memory access time = 1000 ns,
10 hit ratio = 0.9
Memory 1 miss : 1 x 1000 ns
Cache 1000 ns,
9 hit : 9 x 100 ns 1900 ns / 10 = 190 ns 5

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Mapping
The transformation of data from main memory to cache memory
1) Associative mapping
2) Direct mapping
3) Set-associative mapping
Example of cache memory : Fig. 12-10
main memory : 32 K x 12 bit word (15 bit address lines)
cache memory : 512 x 12 bit word M a in m e m o r y
32K 12 C a c h e m e m o ry
CPU
512 12
CPU sends a 15-bit address to cache
Hit : CPU accepts the 12-bit data from cache
Miss : CPU reads the data from main memory (then data is written to cache)
Associative mapping : Fig. 12-11 Cache Coherence (Sec. 13-5)
Cache memory associative memory C P U a d d r e s s ( 1 5 b its )

Address Data Cache memory A r g u m e n t r e g is te r

Direct mapping : Fig. 12-12 A d d re s s D a ta

0 1 0 0 0 3 4 5 0

Cache memory memory 0 2 7 7 7 6 7 1 0

Tag field (n - k) Index field (k) 2 2 3 4 5 1 2 3 4

2k words cache memory + 2n words main memory

Tag = 6 bit (15 - 9), Index = 9 bit

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6 b its 9 b its
Tag In d e x

Tag (6 bit)
00 - 63
00 000 000
512 12
32K 12
C a c h e m e m o ry
Index (9 bit) O c ta l
H ex M a in m e m o r y a d d re s s
000 - 511 A d d re s s
A d d r e s s = 9 b its
D a ta = 1 2 b its
1FF
A d d r e s s = 1 5 b its
3F 1FF D a ta = 1 2 b its

M e m o ry In d e x
a d d re s s M e m o ry d a ta a d d re s s Tag D a ta
Direct mapping cache organization : Fig. 12-13 000000 1 2 2 0 000 00 1 2 2 0

: 02000 00777 2 3 4 0
1) Index 000 cache 01000 3 4 5 0
2) Tag cache
3) 000 Index cache tag 00
01777 4 5 6 0 777 02 6 7 1 0
(02 )
02000 5 6 7 0
4) miss (b ) C a c h e m e m o ry
5) main memory data read
02777 6 7 1 0
(address 02000 = 5670 read)

( a ) M a in m e m o ry

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Direct mapping cache with block size of 8 words : Fig. 12-14

64 block x 8 word = 512 cache words size
8 word 1 block update

In d e x Tag D a ta 6 6 3
In d e x Tag D a ta Tag D a ta
000 0 1 3 4 5 0 Tag B lo c k W o rd
B lo c k 0 000 0 1 3 4 5 0 0 2 5 6 7 0
007 0 1 6 5 7 8
In d e x
010
B lo c k 1
017

770 0 2
B lo c k 6 3 777 0 2 6 7 1 0 0 0 2 3 4 0
777 0 2 6 7 1 0

Set-associative mapping : Fig. 12-15 (two-way)

Direct mapping ( Fig. 12-13(b)) Index tag
( 02777, 01777 )
set .

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Replacement Algorithm : cache miss or full

1) LRU (Least Recently Used) : block
2) LFU (Least Frequently Used) : block
3) FIFO (First-In First-Out) : block

Writing to Cache : Cache Coherence(Sec. 13-5) Cache READ

Cache (WRITE) , Cache block
main memory update

Main memory Cache memory : ( )

1) Write-through : Cache write main memory write .

2) Write-back : Cache write flag set block
flag write .
Write-back main memory .

Cache Initialization
Cache is initialized : cache empty invalid data .
1) when power is applied to the computer
2) when main memory is loaded with a complete set of programs from auxiliary memory
valid bit
indicate whether or not the word contains valid data

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12-6 Virtual Memory

Virtual Memory : Auxiliary memory Main memory
Translate program-generated (Aux. Memory) address into main memory location
Give programmers the illusion that they have a very large memory, even though the
computer actually has a relatively small main memory
: Intel Pentium Processor
Physical Address Lines = A0 - A31 : 232 = 230 X 22 = 4 Giga
Logical Address = 46 bits address : 2 46 = 240 X 26 = 64 Tera
Address Space & Memory Space
A u x ilia r y m e m o r y
Address Space : Virtual Address
Address used by a programmer M a in m e m o r y

Memory Space : Physical Address(Location) P ro g ra m 1

P ro g ra m 1
D a ta 1 , 1
Address in main memory
D a ta 1 , 2
: Fig. 12-16
D a ta 1 , 1
address space (N) = 1024 K = 220 P ro g ra m 2
D a ta 2 , 1
Auxiliary Memory M e m o ry s p a c e
M = 3 2 K = 2 15
memory space (M) = 32 K = 215
A d d re s s s p a c e
main Memory N = 1 0 2 4 K = 2 20

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Memory table for mapping a virtual address : Fig. 12-17

Translate the 20 bits Virtual address into the 15 bits Physical address
V ir tu a l a d d r e s s

V ir tu a l M a in m e m o r y
a d d re s s M e m o ry a d d re s s M a in
r e g is te r m a p in g r e g is te r m e m o ry
( 2 0 b its ) ta b le ( 1 5 b its )

M e m o r y ta b le M a in m e m o r y
b u f f e r r e g is te r b u f f e r r e g is te r

Address Mapping Using Pages : Fig. 12-18 Page 0

Page 1
Address mapping Page 2
Address space memory space fixed size Page 3
Page 4 B lo c k 0

Page 5 B lo c k 1
Address space : 1 K page
Page 6 B lo c k 2
Memory space : 1 k block Page 7 B lo c k 3
Address space 4 page memory space A d d re s s s p a c e M e m o ry s p a c e
block . N = 8 K = 213 M = 4 K = 212

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Memory table in a paged system : Fig. 12-19

Page no.
L in e n u m b e r
1 0 1 0 1 0 1 0 1 0 0 1 1 V ir tu a l a d d r e s s

T a b le P re s e n c e
a d d re s s b it
000 0 M a in m e m o r y
001 11 1 B lo c k 0
010 00 1 B lo c k 1
011 10 01 0101010011 B lo c k 2
100 0 M a in m e m o r y B lo c k 3
101 01 1 a d d r e s s r e g is te r
110 10 1
MBR
111 10

01 1

M e m o r y p a g e ta b le

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Associative memory page table : Fig. 12-20

Associative memory block number(01)

V ir tu a l m e m o r y

P age no .

1 0 1 L in e n u m b e r A r g u m e n t r e g is te r

1 1 1 0 0 K e y r e g is te r

0 0 1 1 1
0 1 0 0 0
A s s o c ia tiv e m e m o r y
1 0 1 0 1
1 1 0 1 0

P ag e no . B lo c k n o .

Page(Block) Replacement
Page Fault : the page referenced by the CPU is not in main memory
a new page should be transferred from auxiliary memory to main memory
Replacement algorithm : FIFO LRU

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12-7 Memory Management Hardware

Basic components of a Memory Management Unit
1) Address mapping
2) Common program sharing
3) Program protection

MMU : OS
1) CPU
2) memory controller
Segment
A set of logically related instruction or data elements associated with a given
name
: a subroutine, an array of data, a table of symbol, users program

Logical Address
the address generated by a segmented program
similar to virtual address
Virtual Address : fixed-length page
Logical Address : variable-length segment

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Segmented-page MMU
Fig. 12-21(a) : 2 table(segment, page)
2 table
Fig. 12-21(b) : Associative memory 1 table

TLB (Translation Look-a-side Buffer)
associative memory most recently reference table
Numerical Example
: Logical address & Physical address (Fig. 12-22)
Logical Address : 4 8 8
4 bit segment : 16 segments Segm ent Page W o rd

8 bit page : 256 pages ( a ) L o g ic a l a d d r e s s f o r m a t : 1 6 s e g m e n ts o f 2 5 6 p a g e s e a c h ,

e a c h p a g e h a s 2 5 6 w o rd s
8 bit word : 256 address field Address
Physical Address : or Index
12 bit block : 4096 blocks 12 8
8 bit word : 256 address field B lo c k W o rd
2 20 3 2
P h y s ic a l m e m o r y

( b ) P h y s ic a l a d d r e s s f o r m a t : 4 0 9 6 b lo c k s o f 2 5 6 w o r d each,
e a c h w o r d h a s 3 2 b its

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 12-18

: Logical & Physical address assignment (Fig. 12-23)

Logical Address

H e x a d e c im a l Page Table
a d d re s s Page num ber
6 00 00
6 00 FF Page 0 Segm ent Page B lo c k
6 01 00
6 01 FF
Page 1 6 00 012
6 02 00 6 01 000
Page 2
6 02 FF 6 02 019
6 03 00
6 03 FF
Page 3 6 03 053
6 04 00 6 04 A61
Segment 6 04 FF
Page 4

Page ( a ) L o g ic a l a d d r e s s a s s ig n m e n t ( b ) S e g m e n t- p a g e v e r s u s
Word m e m o r y b lo c k a s s ig n m e n t

Block number 019

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 12-19

L o g ic a l a d d r e s s
L o g ic a l a d d r e s s ( in h a x a d e c im a l)
Segm ent Page W o rd 6 02 7E

S e g m e n t ta b le P h y s ic a l m e m o r y
P a g e ta b le
S e g m e n t ta b le P a g e ta b le 0 00
000 00
B lo c k 0
000 FF

6 35
35 012
36 000
+ + 012 00
37 019
B lo c k 1 2
38 053 012 FF
39 A61
F A3

B lo c k W o rd
P h y s ic a l a d d r e s s 019 00
3 2 b it w o r d
019 7E
( a ) L o g ic a l to p h y s ic a l a d d r e s s m a p p in g A3 012 019 FF

( a ) S e g m e n t a n d p a g e ta b le m a p p in g

A r g u m e n t r e g is te r
Segm ent Page B lo c k
Segm ent Page B lo c k
6 02 019
6 04 A61

( b ) A s s o c i a t i v e m e m o r y t r a n s l a t i o n lo o k - a s i d e b u f f e r ( T L B ) ( b ) A s s o c ia tiv e m e m o r y ( T L B )

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 12-20

Memory Protection
Typical segment descriptor : Fig. 12-25

segment Length
B a s e a d d re s s L e n g th P r o te c tio n
Base address

Access Rights : protecting the programs residing in memory

1) Full read and write privileges : no protection
2) Read only : write protection
3) Execute only : program protection
4) System only : operating system protection

Computer System Architecture Chap. 12 Memory Organization Dept. of Info. Of Computer.

 12-21

A d d re s s b u s CPU

16 - 11 10 9 8 7 - 1 RD W R D a ta b u s

Decoder
3 2 1 0
CS1
CS2
128 8 D a ta
RD
RAM 1
W R
AD7

CS1
CS2
128 8 D a ta
RD
RAM 2
W R
AD7

CS1
CS2
128 8 D a ta
RD
RAM 3
W R
AD7

CS1
CS2
128 8 D a ta
RD
RAM 4
W R
AD7

CS1
CS2
1- 7 128 8 D a ta
RO M
8
AD9
9

Computer System Architecture Chap. 12 Memory Organization Dept. of Info. Of Computer.