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Lab 2

The document discusses various shift, rotate, multiply, and divide instructions in x86 assembly language. It explains that logical shifts fill the empty bit position with 0 while arithmetic shifts fill it with the sign bit. The SHL instruction performs a logical left shift. Fast multiplication can be done by left shifting. The SHR instruction performs a logical right shift. The ROL and ROR instructions rotate bits left and right respectively. The MUL instruction multiplies registers and produces double-length results. DIV performs unsigned division with a single operand assumed to be the divisor.

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Sadia Bilal
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© © All Rights Reserved
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Download as PPTX, PDF, TXT or read online on Scribd
192 views

Lab 2

The document discusses various shift, rotate, multiply, and divide instructions in x86 assembly language. It explains that logical shifts fill the empty bit position with 0 while arithmetic shifts fill it with the sign bit. The SHL instruction performs a logical left shift. Fast multiplication can be done by left shifting. The SHR instruction performs a logical right shift. The ROL and ROR instructions rotate bits left and right respectively. The MUL instruction multiplies registers and produces double-length results. DIV performs unsigned division with a single operand assumed to be the divisor.

Uploaded by

Sadia Bilal
Copyright
© © All Rights Reserved
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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Assembly Lab2

Logical Shift
A logical shift fills the newly created bit
position with zero:
0
CF

Irvine, Kip R. Assembly Language


for x86 Processors 7/e, 2015. 2
Arithmetic Shift
An arithmetic shift fills the newly created bit
position with a copy of the numbers sign bit:

CF

Irvine, Kip R. Assembly Language


for x86 Processors 7/e, 2015. 3
SHL Instruction
The SHL (shift left) instruction performs
a logical left shift on the destination
operand, filling the lowest bit with 0.

Operand types for SHL:


SHL reg,imm8 (Same for all shift and
SHL mem,imm8 rotate instructions)
SHL reg,CL
SHL mem,CL

Irvine, Kip R. Assembly Language


for x86 Processors 7/e, 2015. 4
Fast Multiplication
Shifting left 1 bit multiplies a number by 2

Before: 0 0 0 0 0 1 0 1 = 5
mov dl,5
After: 0 0 0 0 1 0 1 0 = 10
shl dl,1

Shifting left n bits multiplies the operand by 2n


For example, 5 * 22 = 20

mov dl,5
shl dl,2 ; DL = 20

Irvine, Kip R. Assembly Language


for x86 Processors 7/e, 2015. 5
SHR Instruction
The SHR (shift right) instruction performs a
logical right shift on the destination operand.
The highest bit position is filled with a zero.
0
CF

Shifting right n bits divides the operand by 2n


mov dl,80
shr dl,1 ; DL = 40
shr dl,2 ; DL = 10

Q: How about 81 shr 1? 40 (81: 0101 0001b)

Irvine, Kip R. Assembly Language


for x86 Processors 7/e, 2015. 6
SAL and SAR Instructions
SAL (shift arithmetic left) is identical to SHL.
SAR (shift arithmetic right) performs a right
arithmetic shift on the destination operand.

CF

An arithmetic shift preserves the number's sign.


mov dl,-80 ; 10110000
sar dl,1 ; DL = -40
sar dl,2 ; DL = -10, 11110110b

Q: How about -81 sar 1? (1010 1111) -41 (1101 0111)

Irvine, Kip R. Assembly Language


for x86 Processors 7/e, 2015. 7
ROL Instruction
ROL (rotate) shifts each bit to the left
The highest bit is copied into both the
Carry flag and into the lowest bit
No bits are lost

CF

mov al,11110000b
rol al,1 ; AL = 11100001b

mov dl,3Fh
rol dl,4 ; DL = F3h

Irvine, Kip R. Assembly Language


for x86 Processors 7/e, 2015. 8
ROR Instruction
ROR (rotate right) shifts each bit to the right
The lowest bit is copied into both the Carry
flag and into the highest bit
No bits are lost

CF

mov al,11110000b
ror al,1 ; AL = 01111000b

mov dl,3Fh
ror dl,4 ; DL = F3h

Irvine, Kip R. Assembly Language


for x86 Processors 7/e, 2015. 9
MUL Instruction
In 32-bit mode, MUL (unsigned multiply) instruction
multiplies an 8-, 16-, or 32-bit operand by either AL, AX,
or EAX.

The instruction formats are:


MUL r/m8
MUL r/m16
MUL r/m32

Irvine, Kip R. Assembly Language


for x86 Processors 7/e, 2015. 10
64-Bit MUL Instruction
In 64-bit mode, MUL (unsigned multiply) instruction
multiplies a 64-bit operand by RAX, producing a 128-bit
product.

The instruction formats are:


MUL r/m64

Example:
mov rax,0FFFF0000FFFF0000h
mov rbx,2
mul rbx ; RDX:RAX = 0000000000000001FFFE0001FFFE0000

Irvine, Kip R. Assembly Language


for x86 Processors 7/e, 2015. 11
MUL Examples
100h * 2000h, using 16-bit operands:

.data
val1 WORD 2000h
val2 WORD 100h
.code
mov ax,val1
mul val2 ; DX:AX = 0020 0000h, CF=1

12345h * 1000h, using 32-bit operands:

mov eax,12345h
mov ebx,1000h
mul ebx ; EDX:EAX = 0000000012345000h, CF=0

Irvine, Kip R. Assembly Language


for x86 Processors 7/e, 2015. 12
Benchmarking Two
Multiplications
Comparing Multiplications: CompareMult.asm
mult_by_shifting
mult_by_MUL

What is the result?

How about the result from the text:


Using MUL 241% slow?

Irvine, Kip R. Assembly Language


for Intel-Based Computers 5/e, 13
2007.
DIV Instruction
The DIV (unsigned divide) instruction
performs 8-bit, 16-bit, and 32-bit
division on unsigned integers
A single operand is supplied (register
or memory operand), which is
assumed to be the divisor
Default Operands:
Instruction formats:
DIV reg/mem8
DIV reg/mem16
DIV reg/mem32

Irvine, Kip R. Assembly Language


for x86 Processors 7/e, 2015. 14
DIV Examples
Divide 8003h by 100h, using 16-bit operands:

mov dx,0 ; clear dividend, high


mov ax,8003h ; dividend, low
mov cx,100h ; divisor
div cx ; AX = 0080h, DX = 3

Same division, using 32-bit operands:

mov edx,0 ; clear dividend, high


mov eax,8003h ; dividend, low
mov ecx,100h ; divisor
div ecx ; EAX = 00000080h, EDX = 3

Irvine, Kip R. Assembly Language


for x86 Processors 7/e, 2015. 15
64-Bit DIV Example
Divide 000001080000000033300020h by
00010000h:
.data
dividend_hi QWORD 00000108h
dividend_lo QWORD 33300020h
divisor QWORD 00010000h

.code
mov rdx, dividend_hi
mov rax, dividend_lo
div divisor ; RAX = quotient
; RDX = remainder

RAX (quotient): 0108000000003330h


RDX (remainder): 0000000000000020h

Irvine, Kip R. Assembly Language


for x86 Processors 7/e, 2015. 16

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